A Polar Model for Evidential Reasoning. - Chua-Chin Wang; Hon-Son Don (Inf. Sci., 1994)

A Modified Measure for Fuzzy Subsethood. - Chua-Chin Wang; Hon-Son Don (Inf. Sci., 1994)

A robust continuous model for evidential reasoning. - Chua-Chin Wang; Hon-Son Don (J. Intell. Robotic Syst., 1994)

Realization of bidirectional associative memory using a pseudo-parallel searching approach. - Chua-Chin Wang; In-Hau Horng (ICNN, 1995)

Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. - Chua-Chin Wang; Jeng-Ming Wu (ISCAS, 1995)

An analysis of high-capacity discrete exponential BAM. - Chua-Chin Wang; Hon-Son Don (IEEE Trans. Neural Networks, 1995)

The decision-making properties of discrete multiple exponential bidirectional associative memories. - Chua-Chin Wang; Jyh-Ping Lee (IEEE Trans. Neural Networks, 1995)

Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory. - Chua-Chin Wang (J. Inf. Sci. Eng., 1996)

Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory. - Chua-Chin Wang; Shiou-Ming Hwang; Jyh-Ping Lee (IEEE Trans. Syst. Man Cybern. Part B, 1996)

Digital Design of Discrete Exponential Bidirectional Associative Memory. - Chua-Chin Wang; Chih-Lwan Fan (J. VLSI Signal Process., 1997)

Fuzzy data recall using polynomial bidirectional hetero-correlator. - Chua-Chin Wang; Cheng-Fa Tsai (SMC, 1998)

The Majority Theorem of Centralized Multiple BAMs Networks. - Chua-Chin Wang; Hon-Son Don (Inf. Sci., 1998)

Data compression by the recursive algorithm of exponential bidirectional associative memory. - Chua-Chin Wang; Chang-Rong Tsai (IEEE Trans. Syst. Man Cybern. Part B, 1998)

Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. - Chua-Chin Wang; Sheng-Hua Chen; Shen-Fu Hsiao; Chuan-Lin Wu (ICECS, 1999)

A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (ISCAS (2), 1999)

Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator. - Chua-Chin Wang; Cheng-Fa Tsai (ISCAS (5), 1999)

A Novel Neural Architecture with High Storage Capacity. - Chua-Chin Wang; Cheng-Fa Tsai (IJCNN (5), 2000)

Design of an inter-plane circuit for clocked PLAs. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (ISCAS, 2000)

Improved design of C2PL 3-2 compressors with less transistor count. - Chua-Chin Wang; Po-Ming Lee; Chenn-Jung Hunng (ISCAS, 2000)

A fast dynamic 64-bit comparator with small transistor count. - Chua-Chin Wang; Hsin-Long Wu; Chih-Feng Wu (ISCAS, 2000)

Fuzzy data processing using polynomial bidirectional hetero-associative network. - Chua-Chin Wang; Cheng-Fa Tsai (Inf. Sci., 2000)

Single-ended SRAM with high test coverage and short test time. - Chua-Chin Wang; Chi-Feng Wu; Rain-Ted Hwang; Chia-Hsiung Kao (IEEE J. Solid State Circuits, 2000)

A deterministic capacity-finding method for multi-valued exponential BAM. - Chua-Chin Wang; Chenn-Jung Huang; Shiou-Ming Hwang (IEEE Trans. Syst. Man Cybern. Part A, 2000)

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (VLSI Design, 2000)

Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library. - Chua-Chin Wang; Chenn-Jung Huang; I-Yen Chang (VLSI Design, 2000)

Design and Analysis of Digital Ratioed Compressors for Inner Product Processing. - Chua-Chin Wang; Chenn-Jung Huang; Po-Ming Lee (VLSI Design, 2000)

Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs. - Chua-Chin Wang; Chih-Chiang Chiu; Yu-Tsung Chien (ICECS, 2001)

An area-saving 3-dimensional decoder structure for ROMs. - Chua-Chin Wang; Ya-Hsin Hsueh; Ying-Pei Chen (ICECS, 2001)

Design of a cycle-efficient 64b/32b integer divider using a table-sharing method. - Chua-Chin Wang; Po-Ming Lee; Jun-Jie Wang; Chenn-Jung Huang (ICECS, 2001)

A 1.0 GHz clock generator design with a negative delay using a single-shot locking method. - Chua-Chin Wang; Yih-Long Tseng; Rong-Sui Kao (ICECS, 2001)

A 1.25 GHz 32-bit tree-structured carry lookahead adder. - Chua-Chin Wang; Po-Ming Lee; Rong-Chin Lee; Chenn-Jung Huang (ISCAS (4), 2001)

A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems. - Chenn-Jung Huang; Wei Kuang Lai; Chua-Chin Wang; Yu-Jyr Jin; Hsin Wei Chen (Comput. Commun., 2001)

Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. - Chua-Chin Wang; Cheng-Fa Tsai; Yu-Tsun Chien (J. Inf. Sci. Eng., 2001)

6-T SRAM using dual threshold voltage transistors and low-power quenchers. - Chua-Chin Wang; Po-Ming Lee; Kuo-Long Chen (ICECS, 2002)

A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula. - Chua-Chin Wang; Hsien-Chih She; Ron Hu (ICECS, 2002)

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. - Chua-Chin Wang; Hsien-Chih She; Ron Hu (ICECS, 2002)

Image Processing Techniques for Wafer Defect Cluster Identification. - Chenn-Jung Huang; Chua-Chin Wang; Chi-Feng Wu (IEEE Des. Test Comput., 2002)

A low-cost plasma display panel data dispatcher for image enhancement. - Chua-Chin Wang; Ya-Hsin Hsueh; Chiuan-Shian Chen; Jih-Fon Huang (IEEE Trans. Consumer Electron., 2002)

Design of an Inter-plane Circuit for Clocked PLAs. - Chua-Chin Wang; Ya-Hsin Hsueh; Yu-Tsun Chien; Ying-Pei Chen (VLSI Design, 2002)

An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method. - Chua-Chin Wang; Ya-Hsin Hsueh; Shao-Ku Huang (VLSI Design, 2002)

A Fast Dynamic 64-bit Comparator with Small Transistor Count. - Chua-Chin Wang; Ya-Hsin Hsueh; Hsin-Long Wu; Chih-Feng Wu (VLSI Design, 2002)

Improved Design of C2PL 3-2 Compressors for Inner Product Processing. - Chua-Chin Wang; Po-Ming Lee; Chenn-Jung Huang (VLSI Design, 2002)

A boosted wordline voltage generator for low-voltage memories. - Chua-Chin Wang; Ya-Hsin Hsueh; Ting-Wan Kuo; Ron Hu (ICECS, 2003)

Dual-polarity high voltage generator design for non-volatile memories. - Chua-Chin Wang; Yih-Long Tseng; Tian-Hau Chen; Ron Hu (ICECS, 2003)

An SRAM design using dual threshold voltage transistors and low-power quenchers. - Chua-Chin Wang; Po-Ming Lee; Kuo-Long Chen (IEEE J. Solid State Circuits, 2003)

An area-saving decoder structure for ROMs. - Chua-Chin Wang; Ya-Hsin Hsueh; Ying-Pei Chen (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm. - Chua-Chin Wang; Po-Ming Lee; Jun-Jie Wang; Chenn-Jung Huang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A C-less ASK demodulator for implantable neural interfacing chips. - Chua-Chin Wang; Ya-Hsin Hsueh; U. Fat Chio; Yu-Tzu Hsiao (ISCAS (4), 2004)

A phase-adjustable negative phase shifter using a single-shot locking method. - Chua-Chin Wang; Ya-Hsin Hsueh; Sen-Fu Hong; Rong-Sui Kao (ISCAS (2), 2004)

High-PSR bias circuitry for NTSC sync separation. - Chua-Chin Wang; Yih-Long Tseng; Tzung-Je Lee; Ron Hu (ISCAS (1), 2004)

A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. - Chua-Chin Wang; Yih-Long Tseng; Hon-Yuan Leo; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. - Chua-Chin Wang; Yih-Long Tseng; Hsien-Chih She; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. - Chua-Chin Wang; Yih-Long Tseng; Hsien-Chih She; Chih-Chen Li; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. - Chua-Chin Wang; Ching-Li Lee; Li-Ping Lin; Yih-Long Tseng (ISCAS (1), 2005)

Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator. - Chua-Chin Wang; Jian-Ming Huang; Hon-Chen Cheng; Ron Hu (IEEE J. Solid State Circuits, 2005)

Low-Power Small-Area Digital I/O Cell. - Chua-Chin Wang; Ching-Li Lee; Yih-Long Tseng; Chiuan-Shian Chen; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers. - Chua-Chin Wang; Jian-Ming Huang; Hsian-Chang Cheng (IEEE Trans. Consumer Electron., 2005)

Low-cost video decoder with 2D2L comb filter for NTSC digital TVs. - Chua-Chin Wang; Ching-Li Lee; Ming-Kai Chang (IEEE Trans. Consumer Electron., 2005)

A multiparameter implantable microstimulator SOC. - Chua-Chin Wang; Tzung-Je Lee; Yu-Tzu Hsiao; U. Fat Chio; Chi-Chun Huang; J.-J. J. Chin; Ya-Hsin Hsueh (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A temperature-insensitive self-recharging circuitry used in DRAMs. - Chua-Chin Wang; Yih-Long Tseng; Chih-Chiang Chiu (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. - Chua-Chin Wang; Chi-Chun Huang; Tzung-Je Lee; U. Fat Chio (APCCAS, 2006)

A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. - Chua-Chin Wang; Chi-Chun Huang; Jian-Sing Liou; Kuan-Wen Fang (APCCAS, 2006)

An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. - Chua-Chin Wang; Chi-Chun Huang; Tzung-Je Lee; Cheng-Mu Wu; Gang-Neng Sung; Kuan-Wen Fang; Sheng-Lun Tseng; Jia-Jin Chen (APCCAS, 2006)

A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers. - Chua-Chin Wang; Gang-Neng Sung; Ming-Kai Chang; Ching-Li Lee; Cheng-Mu Wu; Ju-Ya Chen (APCCAS, 2006)

Engery-Efficient Double-Edge Triggered Flip-Flop Design. - Chua-Chin Wang; Gang-Neng Sung; Ming-Kai Chang; Ying-Yu Shen (APCCAS, 2006)

Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263. - Chua-Chin Wang; Gang-Neng Sung; Jia-Hao Li (IIH-MSP, 2006)

A 6.57 mW ZigBee transceiver for 868/915 MHz band. - Chua-Chin Wang; Jian-Ming Huang; Chih-Yi Chang; Kuang-Ting Cheng; Chih-Peng Li (ISCAS, 2006)

A 4-Kb low power 4-T SRAM design with negative word-line gate drive. - Chua-Chin Wang; Ching-Li Lee; Wun-Ji Lin (ISCAS, 2006)

A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. - Chua-Chin Wang; Gang-Neng Sung (ISVLSI, 2006)

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. - Chua-Chin Wang; Jian-Ming Huang; Yih-Long Tseng; Wun-Ji Lin; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. - Chua-Chin Wang; Ching-Li Lee; Chun-Yang Hsiao; Jin-Fon Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity. - Chua-Chin Wang; Tzung-Je Lee; Chih-Chen Li; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment. - Chua-Chin Wang; Tzung-Je Lee; Hoi Kam Lo; Shih-Ping Lin 002; Ron Hu (IEEE Trans. Consumer Electron., 2006)

An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier. - Chua-Chin Wang; Chi-Chun Huang; Jian-Sing Liou; Yan-Jhin Ciou; I-Yu Huang; Chih-Peng Li; Yung-Chin Lee; Wen-Jen Wu (ISCAS, 2007)

A Low-power Sensorless Inverter Controller of Brushless DC Motors. - Chua-Chin Wang; Gang-Neng Sung; Kuan-Wen Fang; Sheng-Lun Tseng (ISCAS, 2007)

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator. - Chua-Chin Wang; Tzung-Je Lee; Chih-Chen Li; Ron Hu (Microelectron. J., 2007)

An 80MHz PLL with 72.7ps peak-to-peak jitter. - Chua-Chin Wang; Gang-Neng Sung; Jian-Ming Huang; Li-Ping Lin (Microelectron. J., 2007)

A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme. - Chua-Chin Wang; Ching-Li Lee; Wun-Ji Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Li-ion battery charging design for biomedical implants. - Chi-Chun Huang; Shou-Fu Yen; Chua-Chin Wang (APCCAS, 2008)

A ROM-less DDFS using a nonlinear DAC with an error compensation current array. - Chua-Chin Wang; Chia-Hao Hsu; Tuo-Yu Yao; Jian-Ming Huang (APCCAS, 2008)

A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation. - Jian-Ming Huang; Chia-Chuan Lee; Chua-Chin Wang (ICECS, 2008)

A self-disable sense technique with differential NAND cell for content-addressable memories. - Chi-Chun Huang; Jun-Han Wu; Chua-Chin Wang (ICECS, 2008)

Mixed-voltage I/O buffer using 0.35 μm CMOS technology. - Tzung-Je Lee; Wei-Chih Chang; Chua-Chin Wang (ICECS, 2008)

A 32-bit carry lookahead adder design using complementary all-N-transistor logic. - Gang-Neng Sung; Chun-Ying Juan; Chua-Chin Wang (ICECS, 2008)

A power-aware 2-dimensional bypassing multiplier using cell-based design flow. - Gang-Neng Sung; Yan-Jhin Ciou; Chua-Chin Wang (ISCAS, 2008)

Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. - Tung-Han Tsai; Chin-Lin Chen; Ching-Li Lee; Chua-Chin Wang (ISCAS, 2008)

A mini-invasive multi-function bladder urine pressure measurement system. - Chua-Chin Wang; Chi-Chun Huang; Jun-Han Wu; I-Yu Huang (ISCAS, 2008)

A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. - Chua-Chin Wang; Gang-Neng Sung; Chi-Chun Huang; Ching-Li Lee; Tian-Hau Chen; Wun-Ji Lin; Ron Hu (J. Circuits Syst. Comput., 2008)

A single-chip CMOS IF-band converter design for DVB-T receivers. - Chua-Chin Wang; Chi-Chun Huang; Ching-Li Lee; Chien-Chih Hung; Li-Pin Lin (Microelectron. J., 2008)

A low-power ADPLL using feedback DCO quarterly disabled in time domain. - Chua-Chin Wang; Chi-Chun Huang; Sheng-Lun Tseng (Microelectron. J., 2008)

A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. - Chua-Chin Wang; Tzung-Je Lee; U. Fat Chio; Yu-Tzu Hsiao; Jia-Jin Chen (Microelectron. J., 2008)

A Mini-Invasive Long-Term Bladder Urine Pressure Measurement ASIC and System. - Chua-Chin Wang; Chi-Chun Huang; Jian-Sing Liou; Yan-Jhin Ciou; I-Yu Huang; Chih-Peng Li; Yung-Chin Lee; Weng-Jeng Wu (IEEE Trans. Biomed. Circuits Syst., 2008)

All-MOS ASK Demodulator for Low-Frequency Applications. - Tzung-Je Lee; Ching-Li Lee; Yan-Jhin Ciou; Chi-Chun Huang; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network. - Chua-Chin Wang; Chi-Chun Huang; Jian-Ming Huang; Chih-Yi Chang; Chih-Peng Li (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. - Chua-Chin Wang; Chi-Chun Huang; Ching-Li Lee; Tsai-Wen Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. - Tzung-Je Lee; Chua-Chin Wang (VLSI Design, 2008)

Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection. - Chua-Chin Wang; Gang-Neng Sung; Pai-Li Liu (J. Signal Process. Syst., 2008)

Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology. - Chia-Hao Hsu; Gang-Neng Sung; Tuo-Yu Yao; Chun-Ying Juan; Yain-Reu Lin; Chua-Chin Wang (ISCAS, 2009)

A Drive Circuit for Piezoelectric Devices with Low Harmonics Content. - Shaul Ozeri; Doron Shmilovitz; Chua-Chin Wang (ISCAS, 2009)

Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks. - Sen-Hung Wang; Chih-Peng Li; Chao-Tang Yu; Jian-Ming Huang; Chua-Chin Wang (IEICE Trans. Commun., 2009)

Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology. - Tzung-Je Lee; Tieh-Yen Chang; Chua-Chin Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Low-Power Multiplier Design Using a Bypassing Technique. - Chua-Chin Wang; Gang-Neng Sung (J. Signal Process. Syst., 2009)

A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer. - Ron-Chi Kuo; Hsiao-Han Hou; Chua-Chin Wang (APCCAS, 2010)

A high precision low dropout regulator with nested feedback loops. - Ron-Chi Kuo; Tung-Han Tsai; Yi-Jie Hsieh; Chua-Chin Wang (APCCAS, 2010)

A mini-invasive multi-function biomedical pressure measurement system ASIC. - Chua-Chin Wang; Chi-Chun Huang; Yi-Cheng Liu; Victor Pikov; Doron Shmilovitz (ISCAS, 2010)

A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit. - Chua-Chin Wang; Szu-Chia Liao; Yi-Cheng Liu (ISCAS, 2010)

A low-power 2.45 GHz WPAN modulator/demodulator. - Chua-Chin Wang; Gang-Neng Sung; Jian-Ming Huang; Lung-Hsuan Lee; Chih-Peng Li (Microelectron. J., 2010)

(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. - Chi-Chun Huang; Tzung-Je Lee; Wei-Chih Chang; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

All-Digital Frequency Synthesizer Using a Flying Adder. - Gang-Neng Sung; Szu-Chia Liao; Jian-Ming Huang; Yu-Cheng Lu; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications. - Chua-Chin Wang; Chih-Lin Chen; Ron-Chi Kuo; Doron Shmilovitz (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Self-Disabled Sensing Technique for Content-Addressable Memories. - Chua-Chin Wang; Chia-Hao Hsu; Chi-Chun Huang; Jun-Han Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator. - Chua-Chin Wang; Chia-Hao Hsu; Yi-Cheng Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage. - Chua-Chin Wang; Ron-Chi Kuo; Jen-Wei Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Guest Editorial Special Issue on ISCAS 2009. - Chua-Chin Wang; Felix Lustenberger; Yehia Massoud; Wouter A. Serdijn (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems. - Chua-Chin Wang; Gang-Neng Sung; Po-Cheng Chen; Chin-Long Wey (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Energy-Efficient Double-Edge Triggered Flip-Flop. - Chua-Chin Wang; Gang-Neng Sung; Ming-Kai Chang; Ying-Yu Shen (J. Signal Process. Syst., 2010)

A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems. - Chua-Chin Wang; Chih-Lin Chen; Tai-Hao Yeh; Yi Hu; Gang-Neng Sung (ISCAS, 2011)

A high voltage battery charger with smooth charge mode transition in BCD process. - Shang-Hsien Yang; Jen-Wei Liu; Yihong Wu; Deng-Sian Wang; Chua-Chin Wang (ISCAS, 2011)

A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers. - Shang-Hsien Yang; Chua-Chin Wang (ISOCC, 2011)

A high-efficiency DC-DC buck converter for sub-2×VDD power supply. - Chua-Chin Wang; Chih-Lin Chen; Gang-Neng Sung; Ching-Lin Wang (Microelectron. J., 2011)

A high precision low dropout regulator with nested feedback loops. - Chua-Chin Wang; Ron-Chi Kuo; Tung-Han Tsai (Microelectron. J., 2011)

One-Time-Implantable Spinal Cord Stimulation System Prototype. - Chia-Hao Hsu; Shao-Bin Tseng; Yi-Jie Hsieh; Chua-Chin Wang (IEEE Trans. Biomed. Circuits Syst., 2011)

A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit. - Chua-Chin Wang; Chia-Hao Hsu; Szu-Chia Liao; Yi-Cheng Liu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset. - Chua-Chin Wang; Chia-Hao Hsu; Chia-Chuan Lee; Jian-Ming Huang (J. Signal Process. Syst., 2011)

Linear programmable gain amplifier using reconfiguration local-feedback transconductors. - Tzung-Je Lee; Wen-Je Lu; Wei-Chih Hsiao; Chua-Chin Wang (APCCAS, 2012)

A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems. - Chua-Chin Wang; Tzu-Chiao Sung; Yihong Wu; Chia-Hao Hsu; Doron Shmilovitz (APCCAS, 2012)

A fast FPW allergy analyzer prototype for point of care (POC). - Chia-Hao Hsu; Yue-Da Tsai; Yun-Chi Chen; Ming-Chih Lee; I-Yu Huang; Chua-Chin Wang (ICCE, 2012)

A PLC transceiver design of in-vehicle power line in FlexRay-based automotive communication systems. - Gang-Neng Sung; Chun-Ming Huang; Chua-Chin Wang (ICCE, 2012)

Configurable Active Star design for automobile FlexRay systems. - Chua-Chin Wang; Chih-Lin Chen; Jie-Jyun Li; Chun-Ying Juan (ICCE, 2012)

A high voltage analog multiplexer with digital calibration for battery management systems. - Chih-Lin Chen; Yi Hu; Wayne Luo; Chua-Chin Wang; Chun-Ying Juan (ICICDT, 2012)

On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers. - Chih-Lin Chen; Hsin-Yuan Tseng; Ron-Chi Kuo; Chua-Chin Wang (ICICDT, 2012)

Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process. - Sih-Yu Chen; Chua-Chin Wang (ICICDT, 2012)

Temperature and process compensated clock generator using feedback TPC bias. - Tzung-Je Lee; Doron Shmilovitz; Yi-Jie Hsieh; Chua-Chin Wang (ICICDT, 2012)

A digital over-temperature protector for FlexRay systems. - Chih-Lin Chen; Sheng-Chih Lin; Chua-Chin Wang; Chun-Ying Juan (ISCAS, 2012)

A fast FPW-based protein concentration measurement system. - Chua-Chin Wang; Chia-Hao Hsu; Yue-Da Tsai; Yun-Chi Chen; Ming-Chih Lee; I-Yu Huang (ISCAS, 2012)

Feed-forward Output Swing Prediction AGC with Parallel-Detect Singular-Store Peak Detector. - Shang-Hsien Yang; Chua-Chin Wang (ISCAS, 2012)

A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. - Chih-Lin Chen; Deng-Shian Wang; Jie-Jyun Li; Chua-Chin Wang (ISOCC, 2012)

A slew rate self-adjusting 2×VDD output buffer With PVT compensation. - Chih-Lin Chen; Hsin-Yuan Tseng; Ron-Chi Kuo; Chua-Chin Wang (VLSI-DAT, 2012)

Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector. - Shang-Hsien Yang; Chua-Chin Wang (Microelectron. J., 2012)

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers. - Shang-Hsien Yang; Chua-Chin Wang (Microelectron. J., 2012)

A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition. - Shang-Hsien Yang; Jen-Wei Liu; Chua-Chin Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Signed Array Multiplier with Bypassing Logic. - Chua-Chin Wang; Chia-Hao Hsu; Gang-Neng Sung; Yu-Cheng Lu (J. Signal Process. Syst., 2012)

A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems. - Chih-Lin Chen; Zong-You Hou; Sheng-Chih Lin; Chua-Chin Wang (ICCE, 2013)

High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. - Chih-Lin Chen; Yi-Lun Wu; Chun-Ying Juan; Chua-Chin Wang (ICICDT, 2013)

A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology. - Chua-Chin Wang; Wen-Je Lu; Hsin-Yuan Tseng (ISCAS, 2013)

A low-power transceiver design for FlexRay-based communication systems. - Chua-Chin Wang; Chih-Lin Chen; Jie-Jyun Li; Gang-Neng Sung; Tai-Hao Yeh; Chun-Ying Juan (Microelectron. J., 2013)

A 2×VDD output buffer with PVT detector for slew rate compensation. - Chua-Chin Wang; Wen-Je Lu; Chih-Lin Chen; Hsin-Yuan Tseng; Ron-Chi Kuo; Chun-Ying Juan (Microelectron. J., 2013)

A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique. - Chua-Chin Wang; Tzu-Chiao Sung; Chia-Hao Hsu; Yue-Da Tsai; Yun-Chi Chen; Ming-Chih Lee; I-Yu Huang (Sensors, 2013)

On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers. - Chua-Chin Wang; Chih-Lin Chen; Ron-Chi Kuo; Hsin-Yuan Tseng; Jen-Wei Liu; Chun-Ying Juan (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit. - Chua-Chin Wang; Chih-Lin Chen; Hsin-Yuan Tseng; Hsiao-Han Hou; Chun-Ying Juan (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An all-digital battery capacity monitor using calibrated current estimation approach. - Chua-Chin Wang; Wen-Je Lu; Min-Yu Tseng (APCCAS, 2014)

A 20 GHz power detector with 176 mV/dB conversion gain. - Chua-Chin Wang; Deng-Shian Wang; Shiou-Ya Chen; Chia-Ming Chang (APCCAS, 2014)

32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. - Tzung-Je Lee; Kai-Wei Ruan; Chua-Chin Wang (ICICDT, 2014)

An on-chip high-voltage current sensor for battery module monitoring. - Chua-Chin Wang; Wen-Je Lu; Sheng-Syong Wang (ICICDT, 2014)

A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process. - Chua-Chin Wang; Chiang-Hsiang Liao; Sih-Yu Chen (ISCAS, 2014)

A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems. - Chua-Chin Wang; Wen-Je Lu; Tzu-Chao Wu; Chun-Ying Juan (ISCAS, 2014)

Noninvasive Control of the Power Transferred to an Implanted Device by an Ultrasonic Transcutaneous Energy Transfer Link. - Doron Shmilovitz; Shaul Ozeri; Chua-Chin Wang; Boaz Spivak (IEEE Trans. Biomed. Eng., 2014)

A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard. - Chua-Chin Wang; Chih-Lin Chen; Gang-Neng Sung; Ching-Lin Wang; Chun-Ying Juan (J. Signal Process. Syst., 2014)

10 Mbps high-voltage digital transciever on single die for 50 V voltage swing. - Chua-Chin Wang; Min-Yu Tseng (ASICON, 2015)

A high-voltage Transceiver for electrical vehicle Battery Management Systems. - Chih-Lin Chen; Deng-Shian Wang; Jie-Jyun Li; Chua-Chin Wang (ICCE, 2015)

A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. - Chua-Chin Wang; Tsung-Yi Tsai; Wei Lin (ICICDT, 2015)

A wide range and high conversion gain power detector for frequency shift sensing applications. - Chua-Chin Wang; Deng-Shian Wang; Shiou-Ya Chen; Chia-Ming Chang (MWSCAS, 2015)

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology. - Chua-Chin Wang; Wen-Je Lu; Kai-Wei Juan; Wei Lin; Hsin-Yuan Tseng; Chun-Ying Juan (Microelectron. J., 2015)

Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring. - Chua-Chin Wang; Wen-Je Lu; Tzu-Chao Wu (Microelectron. J., 2015)

A 30 V rail-to-rail operational amplifier. - Chua-Chin Wang; Tsung-Yi Tsai; Wen-Je Lu; Chih-Lin Chen; Yi-Lun Wu (Microelectron. J., 2015)

A ±3.07% frequency variation clock generator implemented using HV CMOS process. - Chua-Chin Wang; Deng-Shian Wang; Tzu-Chiao Sung; Yi-Jie Hsieh; Tzung-Je Lee (Microelectron. J., 2015)

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. - Chua-Chin Wang; Chih-Lin Chen; Zong-You Hou; Yi Hu; Jam-Wem Lee; Wan-Yen Lin; Yi-Feng Chang; Chia-Wei Hsu; Ming-Hsiang Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips. - Chua-Chin Wang; Wen-Je Lu; Tsung-Yi Tsai (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. - Chih-Lin Chen; Deng-Shian Wang; Jie-Jyun Li; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A flyback driver with adaptive switching frequency control for smart lighting1. - Chua-Chin Wang; Zong-You Hou; Teng-Wei Huang (ICCE, 2016)

On-chip accurate primary-side output current estimator for flyback LED driver control. - Zong-You Hou; Teng-Wei Huang; Chua-Chin Wang (ICICDT, 2016)

A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. - Tsung-Yi Tsai; Yan-You Chou; Chua-Chin Wang (ICICDT, 2016)

A nano-scale 2×VDD I/O buffer with encoded PV compensation technique. - Tsung-Yi Tsai; Yu-Lin Teng; Chua-Chin Wang (ISCAS, 2016)

An accurate phase shift detector using bulk voltage boosting technique for sensing applications. - Yu-Ting Tu; Deng-Shian Wang; Chua-Chin Wang (ISCAS, 2016)

Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. - Chua-Chin Wang; Chia-Lung Hsieh (ISOCC, 2016)

A novel frequency-shift readout system for CEA concentration detection application. - Deng-Shian Wang; Yun-Shen Liu; Chua-Chin Wang (ISOCC, 2016)

High-voltage on-chip current sensor design and analysis for battery modules. - Chua-Chin Wang; Zong-You Hou; Wen-Je Lu; Sheng-Syong Wang (IET Circuits Devices Syst., 2016)

A Leakage Compensation Design for Low Supply Voltage SRAM. - Chua-Chin Wang; Deng-Shian Wang; Chiang-Hsiang Liao; Sih-Yu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2016)

High-voltage bidirectional current sensor. - Zong-You Hou; Hsiu-Chun Tsai; Chua-Chin Wang (ASICON, 2017)

State of charge, state of health, and state of function monitoring for EV BMS. - Zong-You Hou; Pang-Yen Lou; Chua-Chin Wang (ICCE, 2017)

A primary-side output current estimator with process compensator for flyback LED drivers. - Zong-You Hou; Zong-Ying Ho; Jhih-Cheng You; Chua-Chin Wang (ISCAS, 2017)

A pipeline ROM-less DDFS using equal-division interpolation. - Tsung-Yi Tsai; Hsiang-Yu Shih; Chua-Chin Wang (ISOCC, 2017)

Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. - Wei Wang; Yuan-Yuan Xu; Chua-Chin Wang (ISOCC, 2017)

A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application. - Wen-Hui Huang; I-Yu Huang; Yu-Shan Tseng; Chia-Hsu Hsieh; Chua-Chin Wang (Microelectron. J., 2017)

A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. - Deng-Shian Wang; Yu-Hsun Su; Chua-Chin Wang (Microelectron. J., 2017)

Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine. - Je-Wei Lan; Chia-Hsu Hsieh; I-Yu Huang; Yu-Cheng Lin; Tsung-Yi Tsai; Chua-Chin Wang (Sensors, 2017)

2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. - Chua-Chin Wang; Zong-You Hou; Kai-Wei Ruan (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. - Tzung-Je Lee; Tsung-Yi Tsai; Wei Lin; U-Fat Chio; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. - Chua-Chin Wang; Zong-You Hou; Ssu-Wei Huang (APCCAS, 2018)

A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection. - Hao-Chun Huang; Deng-Shian Wang; Chua-Chin Wang (ICCE, 2018)

A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. - Chua-Chin Wang; Zong-You Hou; Chih-Lin Chen; Doron Shmilovitz (Circuits Syst. Signal Process., 2018)

A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range. - Chua-Chin Wang; Zong-You Hou; Jhih-Cheng You (Sensors, 2018)

Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. - Chun-Ting Chen; Tsung-Yi Tsai; Yi-Jen Chiu; Chua-Chin Wang (ASICON, 2019)

A Broken Line Detection Circuit for Multi-cell Li-ion Battery Module1. - Pang-Yen Lou; Chien-Hua Chu; Chua-Chin Wang (ICCE, 2019)

A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology. - Nanang Sulistiyanto; Chua-Chin Wang; Robert Rieger (ICICDT, 2019)

A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs. - Tsung-Yi Tsai; Ting-Sheng Wang; Yi-Jen Chiu; Chua-Chin Wang (ICICDT, 2019)

Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology. - Chua-Chin Wang; I-Ting Tseng (ICICDT, 2019)

High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. - Tzung-Je Lee; Chia-Hsin Hsu; Chua-Chin Wang (ISCAS, 2019)

A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load. - Chua-Chin Wang; Guan-Xian Liu (ISCAS, 2019)

500 MHz 90 nm CMOS 2 ( times ) VDD Digital Output Buffer Immunity to Process and Voltage Variations. - Chua-Chin Wang; Tsung-Yi Tsai; Yu-Lin Deng; Tzung-Je Lee (Circuits Syst. Signal Process., 2019)

A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. - Tzung-Je Lee; Tsung-Yi Tsai; Wei Lin; U. Fat Chio; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; Hsiang-Yu Shih (IEEE Trans. Very Large Scale Integr. Syst., 2019)

3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations. - Chua-Chin Wang; Chia-Yi Huang; Chu-Han Lin; Chia-Hung Yeh; Guan-Xian Liu; Yu-Cheng Chou (APCCAS, 2020)

100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*. - Chua-Chin Wang; Shao-Wei Lu (APCCAS, 2020)

2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. - Chua-Chin Wang; Zong-You Hou; Yu-Lin Deng; U. Fat Chio; Wei Wang (J. Circuits Syst. Comput., 2020)

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry. - Chua-Chin Wang; Zong-You Hou; Deng-Shian Wang; Chia-Lung Hsieh (J. Circuits Syst. Comput., 2020)

A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. - Tzung-Je Lee; Ssu-Wei Huang; Chua-Chin Wang (IEEE Trans. Circuits Syst., 2020)

Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. - Chua-Chin Wang; Kuan-Yu Chao; Sivaperumal Sampath; Ponnan Suresh (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Power-effective ROM-less DDFS Design Approach with High SFDR Performance. - Chua-Chin Wang; Nanang Sulistiyanto; Hsiang-Yu Shih; Yu-Cheng Lin; Wei Wang (J. Signal Process. Syst., 2020)

An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset. - Yu-Cheng Chou; Hsin-Hung Chen; Chau-Chang Wang; Hui-Min Chou; Chua-Chin Wang (AICAS, 2021)

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. - Tzung-Je Lee; Wen-Jian Su; Lean Karlo S. Tolentino; Chua-Chin Wang (APCCAS, 2021)

A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. - Tzung-Je Lee; Wen-Shou Yang; Chua-Chin Wang (APCCAS, 2021)

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. - Uday Kiran Naidu Ekkurthi; Venkatesh Dasari; Jyoshnavi Akiri; Chua-Chin Wang (ISCAS, 2021)

SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction. - Chua-Chin Wang; Chia-Yi Huang; Chia-Hung Yeh (ISCAS, 2021)

67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. - Chua-Chin Wang; Chien-Ping Kuo (ISCAS, 2021)

On-chip CMOS Corner Detector Design for Panel Drivers. - Pang-Yen Lou; Ying-Xuan Chen; Chua-Chin Wang (ISOCC, 2021)

Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer. - Pang-Yen Lou; Yung-Yuan Ho; Chua-Chin Wang (ISOCC, 2021)

2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; Yan-You Chou; Tzung-Je Lee (Circuits Syst. Signal Process., 2021)

High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; I-Yu Huang; Yu-Cheng Lin; Tzung-Je Lee; Guan-Ru Chen (Circuits Syst. Signal Process., 2021)

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. - Chua-Chin Wang; Oliver Lexter July A. Jose; Po-Kai Su; Lean Karlo S. Tolentino; Ralph Gerard B. Sangalang; Jessica Velasco; Tzung-Je Lee (Microelectron. J., 2021)

0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process. - Chua-Chin Wang; Pang-Yen Lou; Zong-You Hou; Hsiu-Chun Tsai (Microelectron. J., 2021)

Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations. - Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process. - Chua-Chin Wang; Chien-Ping Kuo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. - Chua-Chin Wang; Ralph Gerard B. Sangalang; I-Ting Tseng (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. - Chua-Chin Wang; Lean Karlo S. Tolentino; Chia-Yi Huang; Chia-Hung Yeh (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. - Jyoshnavi Akiri; Lean Karlo S. Tolentino; Lung-Jieh Yang; Balasubramanian Esakki; Sivaperumal Sampath; Chua-Chin Wang (APCCAS, 2022)

A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Chua-Chin Wang (APCCAS, 2022)

A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. - Ralph Gerard B. Sangalang; Shih-Heng Luo; Hsin-Che Wu; Bao-Qi He; Shen-Fu Hsiao; Chua-Chin Wang; Chewnpu Jou; Harry Hsia; Douglas C.-H. Yu (APCCAS, 2022)

A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic. - Durga Srikanth Kamarajugadda; Oliver Lexter July A. Jose; Lung-Jieh Yang; Balasubramanian Esakki; Sivaperumal Sampath; Chua-Chin Wang (ICICDT, 2022)

Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. - Tzung-Je Lee; Bo-Hao Liao; Chua-Chin Wang (ICICDT, 2022)

Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. - Shiva Reddy; Ralph Gerard B. Sangalang; Chua-Chin Wang (ICICDT, 2022)

A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. - Li Lin; Lean Karlo S. Tolentino; Chua-Chin Wang (ISCAS, 2022)

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. - Chua-Chin Wang; Ralph Gerard B. Sangalang; Chien-Ping Kuo; Hsin-Che Wu; Yi Hsu; Shen-Fu Hsiao; Chia-Hung Yeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion. - Chia-Hung Yeh; Chu-Han Lin; Li-Wei Kang; Chih-Hsiang Huang; Min-Hui Lin 002; Chuan-Yu Chang; Chua-Chin Wang (IEEE Trans. Neural Networks Learn. Syst., 2022)

2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Jui-Min Kuo; Mitch Ming-Chi Chou; Chua-Chin Wang (APCCAS, 2023)

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo S. Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (APCCAS, 2023)

A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. - Ralph Gerard B. Sangalang; Wei-Zhen Chen; Chua-Chin Wang (APCCAS, 2023)

Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. - Ralph Gerard B. Sangalang; You-Wei Shen; Shiva Reddy; Lean Karlo S. Tolentino; Chua-Chin Wang (ASICON, 2023)

A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process. - Ralph Gerard B. Sangalang; Shih-Heng Luo; Chua-Chin Wang (ICICDT, 2023)

Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. - Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (ISCAS, 2023)

SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. - Oliver Lexter July A. Jose; Jui-Min Kuo; Venkata Naveen Kolakaluri; Chua-Chin Wang (MWSCAS, 2023)

A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. - Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (MWSCAS, 2023)

A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. - Chua-Chin Wang; Ralph Gerard B. Sangalang; I-Ting Tseng; Yi-Jen Chiu; Yu-Cheng Lin; Oliver Lexter July A. Jose (IET Circuits Devices Syst., 2023)

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. - Chua-Chin Wang; Oliver Lexter July A. Jose; Wen-Shou Yang; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Tzung-Je Lee (Circuits Syst. Signal Process., 2023)

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. - Chua-Chin Wang; Lean Karlo S. Tolentino; Shao-Wei Lu; Oliver Lexter July A. Jose; Ralph Gerard B. Sangalang; Tzung-Je Lee; Pang-Yen Lou; Wei-Chih Chang (Integr., 2023)

A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. - Ralph Gerard B. Sangalang; Shiva Reddy; Lean Karlo S. Tolentino; You-Wei Shen; Oliver Lexter July A. Jose; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo Santos Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (AICAS, 2024)

A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. - Cheng-Yao Lo; Lean Karlo Santos Tolentino; Jhih-Ying Ke; Jeffrey S. Walling; Yang Yi 002; Chua-Chin Wang (AICAS, 2024)

A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. - Chua-Chin Wang; Shih-Heng Luo; Hsin-Che Wu; Ralph Gerard B. Sangalang; Chewnpu Jou; Harry Hsia; Lan-Chou Cho (AICAS, 2024)

Active Gate Driver Design Using Differential Timing-based Miller Detector for Power MOSFET. - Pradyumna Vellanki; Venkata Naveen Kolakaluri; Yun-Che Chang; L. S. S. Pavan Kumar Chodisetti; Mitch Ming-Chi Chou; Chua-Chin Wang (APCCAS, 2024)

A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. - Oliver Lexter July A. Jose; Yun-Che Chang; Venkata Naveen Kolakaluri; Celso B. Co; Mitch Ming-Chi Chou; Chua-Chin Wang (ISCAS, 2024)

A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. - Soumika Majumder; Venkata Naveen Kolakaluri; Oliver Lexter July A. Jose; Chua-Chin Wang (ISCAS, 2024)

A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. - Soumika Majumder; Lean Karlo Santos Tolentino; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri; Mitch Ming-Chi Chou; Chua-Chin Wang (ISOCC, 2024)

An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process. - Pradyumna Vellanki; Hung-Che Tseng; Ying-Xuan Chen; L. S. S. Pavan Kumar Chodisetti; Chua-Chin Wang (ISOCC, 2024)

A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Durga Srikanth Kamarajugadda; Oliver Lexter July A. Jose; Pradyumna Vellanki (Integr., 2024)

A single-chip PFM-controlled LED driver with 0.5% illuminance variation. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Pang-Yen Lou; Chen-Cheng-Hung Hung; Pradyumna Vellanki; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Tirso A. Ronquillo (Microelectron. J., 2024)

A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Bo-Hao Liao; Pradyumna Vellanki; Tzung-Je Lee (Microelectron. J., 2024)

A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. - Oliver Lexter July A. Jose; Venkata Naveen Kolakaluri; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. - Chua-Chin Wang; Oliver Lexter July A. Jose; Li Lin; Lean Karlo S. Tolentino; Ralph Gerard B. Sangalang; Anela L. Salvador (Circuits Syst. Signal Process., 2024)

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Jhih-Ying Ke; Cheng-Yao Lo; Tzung-Je Lee; Lean Karlo Santos Tolentino (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 5 Vpp 10-Bit 100MS/s Current-Steering DAC as MZM Drivers of PNN Systems. - L. S. S. Pavan Kumar Chodisetti; Chen-Wei Yen; Pradyumna Vellanki; Yung Hung; Chua-Chin Wang (ICICDT, 2025)

A 10-Bit 100 MS/s VCM-Based Switching Analog-to-Digital Converter for PNN Systems. - Pradyumna Vellanki; Yen-Jung Lin; U. Fat Chio; Chua-Chin Wang (ICICDT, 2025)

A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage. - Chua-Chin Wang; Shih-Heng Luo; Hsin-Che Wu; Ralph Gerard B. Sangalang; Chewnpu Jou; Harry Hsia; Lan-Chou Cho (IEEE Access, 2025)

An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process. - Chua-Chin Wang; Pradyumna Vellanki; Shih-Heng Luo; Ralph Gerard B. Sangalang (Integr., 2025)

Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process. - Chua-Chin Wang; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri (Microelectron. J., 2025)