Using constraint geometry to determine maximum rate pipeline clocking. - Chuan-Hua Chang; Edward S. Davidson; Karem A. Sakallah (ICCAD, 1992)

Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. - Chuan-Hua Chang; Edward S. Davidson; Karem A. Sakallah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Performance optimization of pipeline circuits with latches and wave pipelining. - Chuan-Hua Chang (1996)

Two-Dimensionally Arranged Display Drivers Achieved by OS/Si Structure. - Yusuke Komura; Shoki Miyata; Yuki Okamoto; Yuki Tamatsukuri; Hiroki Inoue; Toshihiko Saito; Munehiro Kozuma; Hidetomo Kobayashi; Tatsuya Onuki; Yuichi Yanagisawa; Toshihiko Takeuchi; Yutaka Okazaki; et al. (VLSI Technology and Circuits, 2023)