A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices. - Chuan-Jia Jhang; Cheng-Xin Xue; Je-Min Hung; Fu-Chun Chang; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices. - Win-San Khwa; Yen-Cheng Chiu; Chuan-Jia Jhang; Sheng-Po Huang; Chun-Ying Lee; Tai-Hao Wen; Fu-Chun Chang; Shao-Ming Yu; Tung-Yin Lee; Meng-Fan Chang (ISSCC, 2022)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips. - Hung-Hsi Hsu; Tai-Hao Wen; Ping-Chun Wu; Chuan-Jia Jhang; De-Qi You; Ping-Cheng Chen; Meng-Fan Chang (MWSCAS, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips. - Ping-Chun Wu; Win-San Khwa; Jui-Jen Wu; Jian-Wei Su; Chuan-Jia Jhang; Ho-Yu Chen; Zhao-En Ke; Ting-Chien Chiu; Jun-Ming Hsu; Chiao-Yen Cheng; Yu-Chen Chen; Chung-Chuan Lo; et al. (IEEE J. Solid State Circuits, 2025)