A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. - Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. - Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)