Wire Retiming for System-on-Chip by Fixpoint Computation. - Chuan Lin 002; Hai Zhou 001 (DATE, 2004)

Retiming for wire pipelining in system-on-chip. - Hai Zhou 001; Chuan Lin 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. - Chuan Lin 002; Hai Zhou 001 (ICCAD, 2005)

Wire retiming as fixpoint computation. - Chuan Lin 002; Hai Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

An efficient retiming algorithm under setup and hold constraints. - Chuan Lin 002; Hai Zhou 001 (DAC, 2006)

A revisit to floorplan optimization by Lagrangian relaxation. - Chuan Lin 002; Hai Zhou 001; Chris C. N. Chu (ICCAD, 2006)

Optimal wire retiming without binary search. - Chuan Lin 002; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Clustering for Processing Rate Optimization. - Chuan Lin 002; Jia Wang 003; Hai Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. - Chuan Lin 002; Hai Zhou 001 (ASP-DAC, 2007)

Retiming for Synchronous Data Flow Graphs. - Nikolaos D. Liveris; Chuan Lin 002; J. Wang; Hai Zhou 001; Prithviraj Banerjee (ASP-DAC, 2007)

Design closure driven delay relaxation based on convex cost network flow. - Chuan Lin 002; Aiguo Xie; Hai Zhou 001 (DATE, 2007)

Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. - Chuan Lin 002; Hai Zhou 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)