FPGA implementation of reconfigurable ADPLL network for distributed clock generation. - Chuan Shan; Eldar Zianbetov; Mohammad Javidan; François Anceau; Mehdi Terosiet; Sylvain Feruglio; Dimitri Galayko; Olivier Romain; Éric Colinet; Jérôme Juillard (FPT, 2011)

Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. - Chuan Shan; Dimitri Galayko; François Anceau (NEWCAS, 2012)

Distributed clock generator for synchronous SoC using ADPLL network. - Eldar Zianbetov; Dimitri Galayko; François Anceau; Mohammad Javidan; Chuan Shan; Olivier Billoint; Anton Korniienko; Éric Colinet; Gérard Scorletti; J. M. Akrea; Jérôme Juillard (CICC, 2013)

On-chip clock error characterization for clock distribution system. - Chuan Shan; Dimitri Galayko; François Anceau (ISVLSI, 2013)

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. - Chuan Shan; Eldar Zianbetov; Weiqiang Yu; François Anceau; Olivier Billoint; Dimitri Galayko (ReConFig, 2013)

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. - Vincent Kerzerho; Serge Bernard; Florence Azaïs; Mariane Comte; Olivier Potin; Chuan Shan; G. Bontorin; Michel Renovell (Microelectron. J., 2013)

"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. - Chuan Shan; François Anceau; Dimitri Galayko; Eldar Zianbetov (ISCAS, 2014)

A reconfigurable distributed architecture for clock generation in large many-core SoC. - Chuan Shan; Dimitri Galayko; François Anceau; Eldar Zianbetov (ReCoSoC, 2014)

Distributed clock generator for globally and locally synchronous chips with a large size. (Générateur distribué d'horloge pour puces globalement et localement synchrones de grande taille). - Chuan Shan (2014)

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. - Chuan Shan; Eldar Zianbetov; François Anceau; Olivier Billoint; Dimitri Galayko (NEWCAS, 2015)

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. - Eugene Koskin; Elena Blokhina; Chuan Shan; Eldar Zianbetov; Orla Feely; Dimitri Galayko (NEWCAS, 2016)

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. - Dimitri Galayko; Chuan Shan; Eldar Zianbetov; Mohammad Javidan; Anton Korniienko; François Anceau; Olivier Billoint; Éric Colinet; Elena Blokhina; Jérôme Juillard (IEEE Trans. Circuits Syst. II Express Briefs, 2019)