Group delay as an estimate of delay in logic. - Jirí Vlach; James A. Barby; Anthony Vannelli; T. Talkhan; C.-J. Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Efficient constrained encoding for VLSI sequential logic synthesis. - Chuanjin Richard Shi; Janusz A. Brzozowski (EURO-DAC, 1992)

A signed hypergraph model of constrained via minimization. - C.-J. Richard Shi (Great Lakes Symposium on VLSI, 1992)

A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems. - Chuanjin Richard Shi; Janusz A. Brzozowski (ASP-DAC, 1995)

Exact Dichotomy-based Constrained Encodi. - Olivier Coudert; C.-J. Richard Shi (ICCD, 1996)

Block-level fault isolation using partition theory and logic minimization techniques. - C.-J. Richard Shi (ASP-DAC, 1997)

Solving constrained via minimization by compact linear programming. - C.-J. Richard Shi (ASP-DAC, 1997)

Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. - Michael W. Tian; Chuanjin Richard Shi (DAC, 1997)

Symbolic analysis of large analog circuits with determinant decision diagrams. - Chuanjin Richard Shi; Xiang-Dong Tan (ICCAD, 1997)

Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning. - C.-J. Richard Shi; Anthony Vannelli; Jirí Vlach (J. Heuristics, 1997)

Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial). - C.-J. Richard Shi (ASP-DAC, 1998)

Automatic Test Generation for Linear Analog Circuits under Parameter Variations. - Chuanjin Richard Shi; Michael W. Tian (ASP-DAC, 1998)

Efficient derivation of exact s-expanded symbolic expressions for behavioral modeling of analog circuits. - Chuanjin Richard Shi; Xiang-Dong Tan (CICC, 1998)

Efficient DC Fault Simulation of Nonlinear Analog Circuits. - Michael W. Tian; Chuanjin Richard Shi (DATE, 1998)

Nonlinear Analog DC Fault Simulation by One-Step Relaxation. - Michael W. Tian; Chuanjin Richard Shi (VTS, 1998)

Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS. - Nihal J. Godambe; Chuanjin Richard Shi (J. Electron. Test., 1998)

Entity Overloading for Mixed-Signal Abstraction in VHDL. - C.-J. Richard Shi (J. Inf. Sci. Eng., 1998)

Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems. - Chuanjin Richard Shi; Janusz A. Brzozowski (ACM Trans. Design Autom. Electr. Syst., 1998)

Symmetry Detection for Automatic Analog-Layout Recycling. - Youcef Bourai; Chuanjin Richard Shi (ASP-DAC, 1999)

Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. - Xiang-Dong Tan; Chuanjin Richard Shi (ASP-DAC, 1999)

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. - Xiang-Dong Tan; Chuanjin Richard Shi; Dragos Lungeanu; Jyh-Chwen Lee; Li-Pen Yuan (DAC, 1999)

Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. - Xiang-Dong Tan; Chuanjin Richard Shi (DATE, 1999)

Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. - Dragos Lungeanu; Chuanjin Richard Shi (ICCAD, 1999)

A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis. - Chuanjin Richard Shi; Janusz A. Brzozowski (Discret. Appl. Math., 1999)

Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. - Chuanjin Richard Shi; Michael W. Tian (ACM Trans. Design Autom. Electr. Syst., 1999)

Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. - Tao Pi; Chuanjin Richard Shi (ASP-DAC, 2000)

Symbolic circuit-noise analysis and modeling with determinant decision diagrams. - Xiang-Dong Tan; Chuanjin Richard Shi (ASP-DAC, 2000)

Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. - Tao Pi; Chuanjin Richard Shi (DAC, 2000)

Layout Compaction for Yield Optimization via Critical Area Minimization. - Youcef Bourai; Chuanjin Richard Shi (DATE, 2000)

Parallel and Distributed VHDL Simulation. - Dragos Lungeanu; Chuanjin Richard Shi (DATE, 2000)

Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. - Chuanjin Richard Shi; Sheldon X.-D. Tan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. - Sheldon X.-D. Tan; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. - Sheldon X.-D. Tan; Chuanjin Richard Shi (DAC, 2001)

Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. - Dragos Lungeanu; Chuanjin Richard Shi (ICCD, 2001)

Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. - Alicia Manthe; Chuanjin Richard Shi (ICCD, 2001)

Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. - Chuanjin Richard Shi; Sheldon X.-D. Tan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. - Vikram Jandhyala; Yong Wang 006; Dipanjan Gope; Chuanjin Richard Shi (ISQED, 2002)

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. - Sheldon X.-D. Tan; Chuanjin Richard Shi (ASP-DAC, 2003)

MCAST: an abstract-syntax-tree based model compiler for circuit simulation. - Bo Wan; Bo P. Hu; Lili Zhou; Chuanjin Richard Shi (CICC, 2003)

Symbolic analysis of analog circuits with hard nonlinearity. - Alicia Manthe; Zhao Li; Chuanjin Richard Shi (DAC, 2003)

Symbolic Analysis of Nonlinear Analog Circuits. - Alicia Manthe; Zhao Li; Chuanjin Richard Shi; Kartikeya Mayaram (DATE, 2003)

SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. - Zhao Li; Chuanjin Richard Shi (ICCAD, 2003)

FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. - Lei Yang 019; Chuanjin Richard Shi (ICCAD, 2003)

Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. - Sambuddha Bhattacharya; Chuanjin Richard Shi (ISCAS (4), 2003)

Automatic analog layout retargeting for new processes and device sizes. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (ISCAS (4), 2003)

Parametric Equivalent Circuit Extraction for VLSI Structures. - Pavel V. Nikitin; Winnie Yam; Chuanjin Richard Shi (VLSI-SOC, 2003)

Efficient DDD-Based Interpretable Symbolic Characterization of Large Analog Circuits. - Sheldon X.-D. Tan; Chuanjin Richard Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

IPRAIL - intellectual property reuse-based analog IC layout automation. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (Integr., 2003)

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. - Sheldon X.-D. Tan; Chuanjin Richard Shi (Integr., 2003)

Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. - Sheldon X.-D. Tan; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. - Sheldon X.-D. Tan; Chuanjin Richard Shi; Jyh-Chwen Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Hierarchical extraction and verification of symmetry constraints for analog layout automation. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Roy Hartono; Chuanjin Richard Shi (ASP-DAC, 2004)

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (ASP-DAC, 2004)

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. - Zhao Li; Ravikanth Suravarapu; Roy Hartono; Sambuddha Bhattacharya; Kartikeya Mayaram; Chuanjin Richard Shi (ASP-DAC, 2004)

Parametric reduced order modeling for interconnect analysis. - Guoyong Shi; Chuanjin Richard Shi (ASP-DAC, 2004)

Correct-by-construction layout-centric retargeting of large analog designs. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Roy Hartono; Chuanjin Richard Shi (DAC, 2004)

Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. - Bo Wan; Chuanjin Richard Shi (DATE, 2004)

A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. - Zhao Li; Chuanjin Richard Shi (ISCAS (5), 2004)

Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. - Pavel V. Nikitin; Vikram Jandhyala; Daniel A. White; Nathan Champagne; John D. Rockway; Chuanjin Richard Shi; Chuanyi Yang; Yong Wang 006; Gong Ouyang; Rob Sharpe; John W. Rockway (ISQED, 2004)

Circuit level modeling and simulation of mixed-technology systems. - Bo Wan; Pavel V. Nikitin; Chuanjin Richard Shi (SoCC, 2004)

Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. - Sheldon X.-D. Tan; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

An FPGA implementation of low-density parity-check code decoder with multi-rate capability. - Lei Yang 019; Manyuan Shen; Hui Liu 011; Chuanjin Richard Shi (ASP-DAC, 2005)

Template-driven parasitic-aware optimization of analog integrated circuit layouts. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Chuanjin Richard Shi (DAC, 2005)

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. - Zhao Li; Chuanjin Richard Shi (DATE, 2005)

VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. - Lei Yang 019; Hui Liu 011; Chuanjin Richard Shi (GLOBECOM, 2005)

Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. - Lei Yang 019; Cherry Wakayama; Chuanjin Richard Shi (ACM Great Lakes Symposium on VLSI, 2005)

Fast-yet-accurate PVT simulation by combined direct and iterative methods. - Bo Hu; Chuanjin Richard Shi (ICCAD, 2005)

Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. - Bo Hu; Zhao Li; Lili Zhou; Chuanjin Richard Shi; Kwang-Hyun Baek; Myung-Jun Choe (ISCAS (6), 2005)

Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. - Vikram Jandhyala; Yasuo Kuga; David J. Allstot; Chuanjin Richard Shi (MSE, 2005)

Automatic Device Layout Generation for Analog Layout Retargeting. - Roy Hartono; Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Chuanjin Richard Shi (VLSI Design, 2005)

Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications. - Guoyong Shi; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. - Lili Zhou; Cherry Wakayama; Nuttorn Jangkrajarng; Bo Hu; Chuanjin Richard Shi (ASP-DAC, 2006)

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. - Nuttorn Jangkrajarng; Lihong Zhang; Sambuddha Bhattacharya; Nathan Kohagen; Chuanjin Richard Shi (ICCAD, 2006)

Improved automatic differentiation method for efficient model compiler. - Bo Hu; Chuanjin Richard Shi (ISCAS, 2006)

FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. - Lei Yang 019; Chuanjin Richard Shi (Integr., 2006)

Multilevel symmetry-constraint generation for retargeting large analog layouts. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. - Zhao Li; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings. - Zhao Li; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

On symbolic model order reduction. - Guoyong Shi; Bo Hu; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. - Chuanjin Richard Shi; Michael W. Tian; Guoyong Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. - Lei Yang 019; Hui Liu 011; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A Graph Reduction Approach to Symbolic Circuit Analysis. - Guoyong Shi; Weiwei Chen; Chuanjin Richard Shi (ASP-DAC, 2007)

Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. - Ming Su; Lili Zhou; Chuanjin Richard Shi (ICCD, 2007)

Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. - Lili Zhou; Cherry Wakayama; Robin Panda; Nuttorn Jangkrajarng; Bo Hu; Chuanjin Richard Shi (ICCD, 2007)

VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. - Pavel V. Nikitin; Chuanjin Richard Shi (Integr., 2007)

CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. - Lili Zhou; Cherry Wakayama; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Symmetry-aware placement with transitive closure graphs for analog layout design. - Lihong Zhang; Chuanjin Richard Shi; Yingtao Jiang (ASP-DAC, 2008)

Scalable Symbolic Model Order Reduction. - Yiyu Shi 001; Lei He 001; Chuanjin Richard Shi (BMAS, 2008)

A 6-11GHz multi-phase VCO design with active inductors. - Yu-Te Liao; Chuanjin Richard Shi (ISCAS, 2008)

A quantum-dot light-harvesting architecture using deterministic phase control. - Cherry Wakayama; Wolf Kohn; Zelda B. Zabinsky; Chuanjin Richard Shi (ISCAS, 2008)

Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. - Bo Hu; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. - Lihong Zhang; Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes. - Lingzhi Liu; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. - Chuanjin Richard Shi (ISCAS, 2010)

Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits. - Lihong Zhang; Yuping Zhang; Yingtao Jiang; Chuanjin Richard Shi (Int. J. Circuit Theory Appl., 2010)

Low-power LDPC decoding based on iteration prediction. - Xinmiao Zhang 001; Fang Cai; Richard Shi (ISCAS, 2012)

On the implementation of modified fuzzy vault for biometric encryption. - Xinmiao Zhang 001; Richard Shi; James A. Ritcey (ITA, 2012)

Reducing the latency of Lee-O'Sullivan interpolation through modified initialization. - Xinmiao Zhang 001; Richard Shi; James A. Ritcey (ITA, 2013)

Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. - Chong Li; Suriyaprakash Natarajan; Chuanjin Richard Shi (ICECS, 2015)

A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. - Aili Wang 002; Allen Waters; Chuanjin Richard Shi (ISCAS, 2016)

Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. - Allen Waters; Aili Wang 002; Chuanjin Richard Shi (ISCAS, 2016)

OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Rui Ma; Peiyong Zhang; Xiaolang Yan; Yu Wang 046; Mingyu Wang 001; Hao Min; Chuanjin Richard Shi (ESSCIRC, 2017)

Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. - Aili Wang 002; Chixiao Chen; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting. - Yu Wang 046; Na Yan; Hao Min; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Exploring the programmability for deep learning processors: from architecture to tensorization. - Chixiao Chen; Huwan Peng; Xindi Liu; Hongwei Ding; Chuanjin Richard Shi (DAC, 2018)

Constrained Optimization Based Low-Rank Approximation of Deep Neural Networks. - Chong Li; Chuanjin Richard Shi (ECCV (10), 2018)

iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. - Chixiao Chen; Xindi Liu; Huwan Peng; Hongwei Ding; Chuanjin Richard Shi (ESSCIRC, 2018)

Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. - Ailing Piao; Aili Wang 002; Chuanjin Richard Shi (ISCAS, 2018)

A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems. - Yingfei Xiang; Yu Wang 046; Chuanjin Richard Shi (ISOCC, 2018)

A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. - Yu Wang 046; Dawei Ye; Liangjian Lyu; Yingfei Xiang; Hao Min; Chuanjin Richard Shi (ISSCC, 2018)

Plenaries. - Marcel Urban; Sachin S. Sapatnekar; Richard Shi (SMACD, 2018)

OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Yu Wang 046; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. - Aili Wang 002; Chuanjin Richard Shi (Integr., 2018)

A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (ASP-DAC, 2019)

A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. - Aili Wang 002; Chixiao Chen; Chuanjin Richard Shi (CICC, 2019)

Hierarchical Representation Learning for Bipartite Graphs. - Chong Li; Kunyang Jia; Dan Shen; Chuanjin Richard Shi; Hongxia Yang (IJCAI, 2019)

A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (ISCAS, 2019)

A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. - Dawei Ye; Rongjin Xu; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2019)

A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (ISSCC, 2019)

iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. - Chixiao Chen; Xindi Liu; Huwan Peng; Hongwei Ding; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. - Chuanjin Richard Shi; Aili Wang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. - Shiwei Liu 002; Haozhe Zhu; Chixiao Chen; Lihua Zhang; Chuanjin Richard Shi (AICAS, 2020)

ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM. - Yitu Wang; Fan Chen 001; Linghao Song; Chuanjin Richard Shi; Hai Helen Li; Yiran Chen 001 (DATE, 2020)

A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. - Yuting Tu; Rongjin Xu; Dawei Ye; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2020)

The impact of real-time clinical alerts on the compliance of anesthesia documentation: A retrospective observational study. - Luis E. Tollinche; Richard Shi; Margaret Hannum; Patrick J. McCormick; Alisa Thorne; Kay See Tan; Gloria Yang; Meghana Mehta; Cindy B. Yeoh (Comput. Methods Programs Biomed., 2020)

Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture. - Haozhe Zhu; Yu Wang 046; Chuanjin Richard Shi (IEEE Des. Test, 2020)

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. - Haozhe Zhu; Chixiao Chen; Shiwei Liu 002; Qiaosha Zou; Mingyu Wang 001; Lihua Zhang; Xiaoyang Zeng; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. - Liangjian Lyu; Yu Wang 046; Chixiao Chen; Chuanjin Richard Shi (Integr., 2020)

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. - Dawei Ye; Yu Wang 046; Yingfei Xiang; Liangjian Lyu; Hao Min; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2020)

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. - Liangjian Lyu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Biomed. Circuits Syst., 2020)

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. - Liangjian Lyu; Dawei Ye; Rongjin Xu; Geng Mu; Heng Zhao; Yingfei Xiang; Yuting Tu; Yiyun Zhang; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. - Aili Wang 002; Chuanjin Richard Shi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. - Dawei Ye; Yuting Tu; Wenjun Gong; Rongjin Xu; Chuanjin Richard Shi (A-SSCC, 2021)

An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. - Geng Mu; Dawei Ye; Liangjian Lyu; Xiaobin Zhao; Chuanjin Richard Shi (CICC, 2021)

Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. - Shiwei Liu 002; Zihao Zhao; Yanhong Wang; Qiaosha Zou; Yiyun Zhang; Chuanjin Richard Shi (ACM Great Lakes Symposium on VLSI, 2021)

Single-Pass On-Line Event Detection in Twitter Streams. - Xingfa Qiu; Qiaosha Zou; Chuanjin Richard Shi (ICMLC, 2021)

A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. - Chang Liu; Chun Zhao; Chuanjin Richard Shi (ISCAS, 2021)

A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2021)

Saliency-based YOLO for single target detection. - Junying Hu; Chuanjin Richard Shi; Jiang-She Zhang 001 (Knowl. Inf. Syst., 2021)

Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications. - Chang Liu; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. - Renze Gan; Liangjian Lyu; Geng Mu; Chuanjin Richard Shi (CICC, 2022)

A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. - Rongjin Xu; Dawei Ye; Sirou Li; Chuanjin Richard Shi (ISSCC, 2022)

The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. - Zihao Zhao; Yanhong Wang; Qiaosha Zou; Tie Xu; Fangbo Tao; Jiansong Zhang 001; Xiaoan Wang; Chuanjin Richard Shi; Junwen Luo; Yuan Xie 001 (CoRR, 2022)

A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (Integr., 2022)

Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". - Dawei Ye; Rongjin Xu; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2022)

Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. - Rongjin Xu; Dawei Ye; Chuanjin Richard Shi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos. - Yanhong Wang; Qiaosha Zou; Yanmin Tang; Qing Wang; Jing Ding; Xin Wang; Chuanjin Richard Shi (IEEE Trans. Hum. Mach. Syst., 2022)

A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. - Jingsen Yang; Liangjian Lyu; Zirui Dong; Heyu Ren; Chuanjin Richard Shi (A-SSCC, 2023)

A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. - Renze Gan; Liangjian Lyu; Chuanjin Richard Shi (ESSCIRC, 2023)

Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models. - Huwan Peng; Scott Davidson 004; Richard Shi; Shuaiwen Leon Song; Michael B. Taylor (CoRR, 2023)

Augmenting aspect-level sentiment classification with distance-related local context input. - Yongchuan Dong; Qiaosha Zou; Chuanjin Richard Shi (J. Supercomput., 2023)

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices. - Yanhong Wang; Zihao Zhao; Xu Jin; Haotian Zheng; Maohua Nie; Qiaosha Zou; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Distributed GNN Training by Codes. - Yanhong Wang; Tianchan Guan; Dimin Niu; Qiaosha Zou; Hongzhong Zheng; Chuanjin Richard Shi; Yuan Xie 001 (IEEE Trans. Parallel Distributed Syst., 2023)

A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR. - Heyu Ren; Liangjian Lyu; Binbin Chen; Chuanjin Richard Shi (CICC, 2024)

Timed-Elastic-Band Based Variable Splitting for Autonomous Trajectory Planning. - Hao Zhu; Kefan Jin; Rui Gao; Jialin Wang; Chuanjin Richard Shi (CoRR, 2024)

Fall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar. - Tingxuan Liang; Ruizhi Liu; Lei Yang 019; Yue Lin 009; Chuanjin Richard Shi; Hongtao Xu (Sensors, 2024)

SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification. - Jialin Wang; Rui Gao; Haotian Zheng; Hao Zhu; Chuanjin Richard Shi (IEEE Trans. Neural Networks Learn. Syst., 2024)

ReaLLM: A Trace-Driven Framework for Rapid Simulation of Large-Scale LLM Inference. - Huwan Peng; Scott Davidson 004; C.-J. Richard Shi; Michael B. Taylor (ASAP, 2025)

HCSAs: Hybrid Computing Systolic Arrays for Accelerating Mamba Models with Unified State Space Buffers and Energy-Efficient Dataflow. - Xu Jin; Haotian Zheng; Maohua Nie; Jialin Wang; Chuanjin Richard Shi (ACM Great Lakes Symposium on VLSI, 2025)

LEGO: A 12nm FinFET Analog Cell Library for Analog/Mixed-Signal Applications. - Xindi Liu; Chien-Jian Tseng; Richard Shi (ACM Great Lakes Symposium on VLSI, 2025)

A 40µW 915MHz Receiver with Sub-Passive Third-Harmonic Mixer Achieving -88dBm Sensitivity and Multi-Channel Selection. - Binbin Chen; Heyu Ren; Wenjun Gong; Sirou Li; Liangjian Lyu; C.-J. Richard Shi (ISCAS, 2025)

A 915MHz 97nW Low-Area Wake-Up Receiver with an Envelope-Tracking Mixer Achieving -73.2dBm Sensitivity. - Binbin Chen; Heyu Ren; Wenjun Gong; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2025)

A 240-mV 33.8-μV/°C 1.5-nW Voltage Detector for Energy Harvesting. - Wenjun Gong; Binbin Chen; Liangjian Lyu; C.-J. Richard Shi (ISCAS, 2025)

A 0.473 μJ/class Seizure Detection Processor with LSVM Classifier and LPF-Based Feature Extraction. - Wenxian Gu; Xudong Hao; Hengchang Bi; Xing Wu 005; C.-J. Richard Shi; Liangjian Lyu (ISCAS, 2025)

A Reference Double-Sampling PLL-Based Eight Phase Clock Generator Achieving 0.18mW/GHz/phase and -251.9dB FOMJitter-N. - Sirou Li; Weijia Zeng; Kaiyun Cao; Liangjian Lyu; Chuanjin Richard Shi (ISCAS, 2025)

A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity. - Heyu Ren; Liangjian Lyu; Binbin Chen; Wenjun Gong; Xing Wu 005; Chuanjin Richard Shi (IEEE J. Solid State Circuits, 2025)

A Workload-Balance-Aware Accelerator Enabling Dense-to-Arbitrary-Sparse Neural Networks. - Zihao Zhao; Yanhong Wang; Xu Jin; Haotian Zheng; Maohua Nie; Longfei Gou; Junmin He; Yongchuan Dong; Qiaosha Zou; Yiyun Zhang; C.-J. Richard Shi (ACM Trans. Embed. Comput. Syst., 2025)