An IS Simulation Technique for Very Low BER Performance Evaluation of LDPC Codes. - Enver Cavus; Charles L. Haymes; Babak Daneshrad (ICC, 2006)

A silicon 60GHz receiver and transmitter chipset for broadband communications. - Brian A. Floyd; Scott K. Reynolds; Ullrich R. Pfeiffer; Troy J. Beukema; Janus Grzyb; Chuck Haymes (ISSCC, 2006)

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications. - Scott K. Reynolds; Brian A. Floyd; Ullrich R. Pfeiffer; Troy J. Beukema; Janusz Grzyb; Chuck Haymes; Brian P. Gaucher; Mehmet Soyuer (IEEE J. Solid State Circuits, 2006)

2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link. - Yasunao Katayama; Chuck Haymes; Daiju Nakano; Troy J. Beukema; Brian A. Floyd; Scott K. Reynolds; Ullrich R. Pfeiffer; Brian P. Gaucher; Kai Schleupen (CCNC, 2007)

Low BER performance estimation of LDPC codes via application of importance sampling to trapping sets. - Enver Cavus; Charles L. Haymes; Babak Daneshrad (IEEE Trans. Commun., 2009)

A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. - Sameh W. Asaad; Ralph Bellofatto; Bernard Brezzo; Chuck Haymes; Mohit Kapur; Benjamin D. Parker; Thomas Roewer; Proshanta Saha; Todd Takken; José A. Tierno (FPGA, 2012)

Efficient in-system RTL verification and debugging using FPGAs (abstract only). - Proshanta Saha; Chuck Haymes; Ralph Bellofatto; Bernard Brezzo; Mohit Kapur; Sameh W. Asaad (FPGA, 2012)

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with 100× Speedup in Time-to-Solution and 100, 000× Reduction in Energy-to-Solution. - Andrew S. Cassidy; Rodrigo Alvarez-Icaza; Filipp Akopyan; Jun Sawada; John V. Arthur; Paul Merolla; Pallab Datta; Marc González Tallada; Brian Taba; Alexander Andreopoulos; Arnon Amir; Steven K. Esser; et al. (SC, 2014)

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. - Bharat Sukhwani; Thomas Roewer; Charles L. Haymes; Kyu-Hyoun Kim; Adam J. McPadden; Daniel M. Dreps; Dean Sanner; Jan van Lunteren; Sameh W. Asaad (MICRO, 2017)

Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation. - Bharat Sukhwani; Mohit Kapur; Alda Ohmacht; Liran Schour; Martin Ohmacht; Chris Ward; Chuck Haymes; Sameh W. Asaad (FPGA, 2023)