Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology. - Chuei-Tang Wang; Jeng-Shien Hsieh; Victor C. Y. Chang; En-Hsiang Yeh; Feng-Wei Kuo; Hsu-Hsien Chen; Chih-Hua Chen; Huan-Neng Ron Chen; Ying-Ta Lu; Chewnpu Jou; Hao-Yi Tsai; C. S. Liu; et al. (3DIC, 2015)

Power-Performance Advantages of InFO Technology for Advanced System Integration. - Chuei-Tang Wang; Douglas Yu (3DIC, 2019)

SoIC_H Technology for Heterogenous System Integration. - Chuei-Tang Wang; Chia-Chai Lin; Chih-Hsin Lu; Wei-Ting Chen; Chung-Hao Tsai; Douglas C. H. Yu (VLSI Technology and Circuits, 2022)

A 28-nm 141.4TOPS/W Scalable Reconfigurable Deep Learning SoC for Large-Scale Neural Networks. - I-Hsuan Liu; I-Ting Lin; Yueh-Feng Tsai; Jeng-Sheng Hsieh; Vincent Chen; Chuei-Tang Wang; Chia-Hsiang Yang; Douglas C. H. Yu (A-SSCC, 2024)