Memristor models and circuits for controlling Process-VDD-Temperature variations. - Kwan-Hee Jo; Chul-Moon Jung; Kyeong-Sik Min (ASICON, 2011)

Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes. - Huan Minh Vo; Chul-Moon Jung; Eun-Sub Lee; Kyeong-Sik Min (IEICE Electron. Express, 2011)

Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs. - Huan Minh Vo; Chul-Moon Jung; Eun-Sub Lee; Kyeong-Sik Min (IEICE Electron. Express, 2011)