Energy-Efficient Freshness Transmission Protocol in Wireless Sensor Networks. - Lin He; Yiying Zhang 001; Chulhyun Park; Myong-Soon Park (ScalCom-EmbeddedCom, 2009)

Service Differentiation Using Mobile Femtocell Virtualization. - Eun Kyoung Paik; Sang-Hong Lee; Choongho Lee; Jinyoung Han; Chulhyun Park; Taekyoung Kwon 001; Yanghee Choi (CCNC, 2010)

Outlier detection and countermeasure for hierarchical wireless sensor networks. - Yi-Ying Zhang 001; Han-Chieh Chao; Min Chen 003; Lei Shu 001; Chulhyun Park; Myong-Soon Park (IET Inf. Secur., 2010)

A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. - Mohammad H. Naderi; Chulhyun Park; Suraj Prakash; Martin Kinyua; Eric G. Soenen; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. - Dadian Zhou; Carlos Briseno-Vidrios; Junning Jiang; Chulhyun Park; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. - Chulhyun Park; Tao Chen 006; Kyoohyun Noh; Dadian Zhou; Suraj Prakash; Mohammadhossein Naderi Alizadeh; Aydin I. Karsilayan; Degang Chen 001; Randall L. Geiger; José Silva-Martínez (IEEE Trans. Circuits Syst., 2020)

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method. - Tao Chen 006; Chulhyun Park; Shravan K. Chaganti; José Silva-Martínez; Randall L. Geiger; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2020)

A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. - Tao Chen 006; Chulhyun Park; Hao Meng; Dadian Zhou; José Silva-Martínez; Randall L. Geiger; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2020)

An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC. - Soon-Jae Kweon; Joonho Gil; Chulhyun Park; Sein Oh; Yoontae Jung; Injun Choi; Song-I Cheon; Hung Phan Dang; Ja-Hyuck Koo; Geunhoe Kim; Sohmyung Ha; Minkyu Je (VLSI Circuits, 2021)

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process. - Kyoung-Ub Cho; Joonho Gil; Chulhyun Park; Kyu-Jin Cho; Jaewoo Shin; Eun Seong Kim; Yun Seong Eo; Ramesh Harjani; Nam-Young Kim; Taehyoun Oh (IEEE Access, 2024)