A formal approach to the slack driven scheduling problem in high-level synthesis. - Shih-Hsu Huang; Chun-Hua Cheng (ISCAS (6), 2005)

Three-dimension scheduling under multi-cycle interconnect communications. - Shih-Hsu Huang; Chung-Hsin Chiang; Chun-Hua Cheng (IEICE Electron. Express, 2005)

Operation Scheduling for False Loop Free Circuits. - Shih-Hsu Huang; Chun-Hua Cheng (APCCAS, 2006)

Peak Power Minimization through Power Management Scheduling. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (APCCAS, 2006)

Register binding for clock period minimization. - Shih-Hsu Huang; Chun-Hua Cheng; Yow-Tyng Nieh; Wei-Chieh Yu (DAC, 2006)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. - Shih-Hsu Huang; Chun-Hua Cheng; Chung-Hsin Chiang; Chia-Ming Chang 002 (JCIS, 2006)

An ILP Approach to the Slack Driven Scheduling Problem. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Clock Period Minimization with Minimum Delay Insertion. - Shih-Hsu Huang; Chun-Hua Cheng; Chia-Ming Chang 002; Yow-Tyng Nieh (DAC, 2007)

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. - Wei-Ting Yen; Shih-Hsu Huang; Chun-Hua Cheng (EUC Workshops, 2007)

Operation scheduling for the synthesis of false loop free circuits. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Electron. Express, 2007)

Module binding for low power clock gating. - Chun-Hua Cheng; Shih-Hsu Huang; Wen-Pin Tu (IEICE Electron. Express, 2008)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Power-Management Scheduling for Peak Power Minimization. - Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2008)

Timing driven power gating in high-level synthesis. - Shih-Hsu Huang; Chun-Hua Cheng (ASP-DAC, 2009)

Surge Current Minimization in High-level Synthesis. - Jheng-Fu Yeh; Chun-Hua Cheng; Shih-Hsu Huang (ISCAS, 2009)

An ILP approach to surge current minimization in high-level synthesis. - Shih-Hsu Huang; Jheng-Fu Yeh; Chun-Hua Cheng (IEICE Electron. Express, 2009)

Synthesis of Anti-Aging Gated Clock Designs. - Shih-Hsu Huang; Chun-Hua Cheng; Song-Bin Pan (J. Inf. Sci. Eng., 2009)

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. - Shih-Hsu Huang; Chun-Hua Cheng; Da-Chen Tzeng (J. Inf. Sci. Eng., 2009)

Minimum-Period Register Binding. - Shih-Hsu Huang; Chun-Hua Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. - Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2010)

Teaching three-dimensional system-in-package design automation in a semester course. - Shih-Hsu Huang; Wen-Pin Tu; Hua-Hsin Yeh; Chun-Hua Cheng (MSE, 2011)

Accurate TSV Number Minimization in High-Level Synthesis. - Chih-Hung Lee; Shih-Hsu Huang; Chun-Hua Cheng (J. Inf. Sci. Eng., 2011)

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. - Chun-Hua Cheng; Wei-Shuo Tzeng; Shih-Hsu Huang (APCCAS, 2012)

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (ASP-DAC, 2012)

A formal approach to slack-driven high-level synthesis. - Hua-Hsin Yeh; Shih-Hsu Huang; Chun-Hua Cheng (ISCAS, 2012)

Co-synthesis of data paths and clock control paths for minimum-period clock gating. - Wen-Pin Tu; Shih-Hsu Huang; Chun-Hua Cheng (DATE, 2013)

Live demonstration: A low-power high-level synthesis system. - Hua-Hsin Yeh; Chun-Hua Cheng; Shih-Hsu Huang (APCCAS, 2014)

Power-mode-aware buffer synthesis for low-power clock skew minimization. - Shih-Hsu Huang; Chun-Hua Cheng (IEICE Electron. Express, 2016)

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. - Jui-Hung Hung; Shih-Hsu Huang; Chun-Hua Cheng; Hsu-Yu Kao; Wei-Kai Cheng (VTS, 2020)