Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. - Chun-Kai Hsu; Li-Ming Denq; Mao-Yin Wang; Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu (ATS, 2008)

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. - Shin-Shiun Chen; Chun-Kai Hsu; Hsiu-Chuan Shih; Jen-Chieh Yeh; Cheng-Wen Wu (ASP-DAC, 2013)

Test data analytics - Exploring spatial and test-item correlations in production test data. - Chun-Kai Hsu; Fan Lin; Kwang-Ting Cheng; Wangyang Zhang; Xin Li 001; John M. Carulli; Kenneth M. Butler (ITC, 2013)

Learning from Production Test Data: Correlation Exploration and Feature Engineering. - Fan Lin; Chun-Kai Hsu; Kwang-Ting Cheng (ATS, 2014)

Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction. - Shuangyue Zhang; Fan Lin; Chun-Kai Hsu; Kwang-Ting Cheng; Hong Wang (DATE, 2014)

Feature engineering with canonical analysis for effective statistical tests screening test escapes. - Fan Lin; Chun-Kai Hsu; Kwang-Ting Cheng (ITC, 2014)

Pairwise Proximity-Based Features for Test Escape Screening. - Fan Lin; Chun-Kai Hsu; Alberto Giovanni Busetto; Kwang-Ting Cheng (ICCAD, 2015)

AdaTest: An efficient statistical test framework for test escape screening. - Fan Lin; Chun-Kai Hsu; Kwang-Ting Cheng (ITC, 2015)

Variation and failure characterization through pattern classification of test data from multiple test stages. - Chun-Kai Hsu; Peter Sarson; Gregor Schatzberger; Friedrich Peter Leisenberger; John M. Carulli Jr.; Siddhartha Siddhartha; Kwang-Ting Cheng (ITC, 2016)

Test Data Analytics: Exploration of Hidden Patterns for Test Cost Reduction and Silicon Characterization - Chun-Kai Hsu (2016)