A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. - Chun-Ming Hsu; Matthew Z. Straayer; Michael H. Perrott (ISSCC, 2008)

A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. - Chun-Ming Hsu; Matthew Z. Straayer; Michael H. Perrott (IEEE J. Solid State Circuits, 2008)

Techniques for high-performance digital frequency synthesis and phase control. - Chun-Ming Hsu (2008)

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop. - Belal Helal; Chun-Ming Hsu; Kerwin Johnson; Michael H. Perrott (IEEE J. Solid State Circuits, 2009)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. - Rajesh Inti; Mozhgan Mansuri; Joe Kennedy 001; Hariprasath Venkatram; Chun-Ming Hsu; Aaron Martin; James E. Jaussi; Bryan Casper (VLSI Circuits, 2018)

56G/112G Link Foundations Standards, Link Budgets & Models. - Ganesh Balamurugan; Ajay Balankutty; Chun-Ming Hsu (CICC, 2019)

A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS. - Rajesh Inti; Mozhgan Mansuri; Joe Kennedy 001; Junyi Qiu; Chun-Ming Hsu; Jahnavi Sharma; Hao Li 047; Bryan Casper; James E. Jaussi (CICC, 2021)

A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC. - Hao Li 047; Zhe Xuan; Ranjeet Kumar; Meer Sakib 001; Jahnavi Sharma; Chun-Ming Hsu; Chaoxuan Ma; Haisheng Rong; Ganesh Balamurugan; James E. Jaussi (ECOC, 2021)

11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS. - Hao Li 047; Jahnavi Sharma; Chun-Ming Hsu; Ganesh Balamurugan; James E. Jaussi (ISSCC, 2021)

Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS. - Jahnavi Sharma; Hao Li 047; Zhe Xuan; Ranjeet Kumar; Chun-Ming Hsu; Meer Sakib 001; Peicheng Liao; Haisheng Rong; James E. Jaussi; Ganesh Balamurugan (VLSI Circuits, 2021)

Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and Systems. - Ping-Hsuan Hsieh; Chun-Ming Hsu; Yunzhi Dong (IEEE Open J. Circuits Syst., 2021)

A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS. - Hao Li 047; Chun-Ming Hsu; Jahnavi Sharma; James E. Jaussi; Ganesh Balamurugan (IEEE J. Solid State Circuits, 2022)

A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS. - Mozhgan Mansuri; Rajesh Inti; Joe Kennedy 001; Junyi Qiu; Chun-Ming Hsu; Jahnavi Sharma; Hao Li 047; Bryan Casper; James E. Jaussi (IEEE J. Solid State Circuits, 2022)

Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS. - Jahnavi Sharma; Zhe Xuan; Hao Li 047; Taehwan Kim; Ranjeet Kumar; Meer N. Sakib; Chun-Ming Hsu; Chaoxuan Ma; Haisheng Rong; Ganesh Balamurugan; James E. Jaussi (IEEE J. Solid State Circuits, 2022)