The design and implementation of DCT/IDCT chip with novel architecture. - Kuo-Hsing Cheng; Chih-Sheng Huang; Chun-Pin Lin (ISCAS, 2000)

CIC signal processing embedded system a modulizable platform for multi-domain signal processing. - Chih-Ting Kuo; Chun-Yu Chen; Yu-Tsang Chang; Chun-Pin Lin; Chien-Ming Wu; Chun-Ming Huang (EMBC, 2012)

A novel design methodology for hybrid process 3D-IC. - Chien-Lin Huang; Nian-Shyang Chang; Chi-Shi Chen; Chun-Pin Lin; Chien-Ming Wu; Chun-Ming Huang (VLSI-DAT, 2012)

Morpack Cube: A portable 3D heterogeneous system integration platform. - Chun-Chieh Chiu; Chih-Hsing Lin; Chih-Chyau Yang; Yi-Jun Liu; Ssu-Ying Chen; Jin-Ju Chue; Chih-Ting Kuo; Gang-Neng Sung; Chun-Pin Lin; Chien-Ming Wu; Chun-Ming Huang (SoCC, 2013)

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. - Po-Tsang Huang; Yu-Chieh Huang; Shang-Lin Wu; Yu-Chen Hu; Ming-Wei Lu; Ting-Wei Sheng; Fung-Kai Chang; Chun-Pin Lin; Nien-Shang Chang; Hung-Lieh Chen; Chi-Shi Chen; Jeng-Ren Duann; et al. (ISCAS, 2017)

Universal CMOS Diamond-Graph Circuit for Embedded Computing. - Shun-Wen Cheng; Chun-Pin Lin; Chi-Shi Chen; Wei-Chang Tsai (SoCC, 2018)

21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (ISSCC, 2020)

A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS. - Yu-Tung Liu; ChuKing Kung; Ming-Hang Hsieh; Hsiu-Wen Wang; Chun-Pin Lin; Chao-Yang Yu; Chi-Shi Chen; Tzi-Dar Chiueh (ESSDERC, 2021)

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (IEEE J. Solid State Circuits, 2021)

A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. - Wen-Cong Huang; I-Ting Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (VLSI Technology and Circuits, 2022)

A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. - Yen-Lung Chen; Chung-Hsuan Yang; Yi-Chung Wu; Chao-Hsi Lee; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Jui-Hung Hung; Chia-Hsiang Yang (ISSCC, 2023)

A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow. - Cheng-Yan Du; Chieh-Fu Tsai; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (ISSCC, 2023)

A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots. - I-Ting Lin; Zih-Sing Fu; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (ISSCC, 2023)

A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality. - Wen-Cong Huang; I-Ting Lin; Ying-Sheng Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. - Yu-Hsuan Tsai; Yi-Cheng Lin; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Shi-Hao Chen; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)

2.5 A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos. - Yu-Chun Ding; Chia-Yu Chang; Chun-Yeh Lin; Hui-Yun Tsai; Hao-Jiun Tu; Kai-Feng Chang; Yu-Ching Su; Tsung-Han Hsieh; Yu-Kuan Jian; Wen-Ching Chen; Nian-Shyang Chang; Chun-Pin Lin; et al. (ISSCC, 2025)

A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots. - I-Ting Lin; Zih-Sing Fu; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2025)