Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. - Yuan-Hsiang Kuo; Chun-Shen Liu; Yu-Cheng Li; Yi-Chang Lu (ICASSP, 2013)

Architecture and circuit design of parallel processing elements for de novo sequence assembly. - Yu-Long Huang; Chun-Shen Liu; Yu-Cheng Li; Yi-Chang Lu (SoCC, 2013)

An FPGA-based quality filter for de novo sequence assembly pipeline. - Chun-Shen Liu; Nae-Chyun Chen; Yu-Cheng Li; Yi-Chang Lu (APCCAS, 2016)