Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate. - Jue-Hsuan Hsiao; Liang-Gee Chen; Tzi-Dar Chiueh; Chun-Te Chen (ISCAS, 1993)

A hardware-oriented design for weighted median filters. - Chun-Te Chen; Liang-Gee Chen; Jue-Hsuan Hsiao (ASP-DAC, 1995)

High throughput CORDIC-based systolic array design for the discrete cosine transform. - Jue-Hsuan Hsiao; Liang-Gee Chen; Tzi-Dar Chiueh; Chun-Te Chen (IEEE Trans. Circuits Syst. Video Technol., 1995)

A self-adjusting weighted median filter for removing impulse noise in images. - Chun-Te Chen; Liang-Gee Chen (ICIP (1), 1996)

A bit-level pipelined VLSI architecture for the running order algorithm. - Chun-Te Chen; Liang-Gee Chen; Jue-Hsuan Hsiao (IEEE Trans. Signal Process., 1997)

A Mobile Ticket Validation by VSS Tech with Time-Stamp. - Chun-Te Chen; Te-Chung Lu (EEE, 2004)

An Approach of Digital Rights Management for E-Museum with Enforce Context Constraints in RBAC Environments. - Chun-Te Chen; Kun-De Lin; Ying-Chieh Wu; Kun-Lin Lee (SMC, 2006)

Construction of the Enterprise-level RFID Security and Privacy Management Using Role-Based Key Management. - Chun-Te Chen; Kun-Lin Lee; Ying-Chieh Wu; Kun-De Lin (SMC, 2006)