A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering. - Tze-Yun Sung; Yaw-Shih Shieh; Chun-Wang Yu; Hsi-Chin Hsin (PDCAT, 2006)

Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters. - Tze-Yun Sung; Yaw-Shih Shieh; Chun-Wang Yu; Hsi-Chin Hsin (PDCAT, 2006)

High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation. - Tze-Yun Sung; Yaw-Shih Shieh; Chun-Wang Yu; Hsi-Chin Hsin (PDCAT, 2006)