An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (Asian Test Symposium, 2001)

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (HLDVT, 2001)

An AVPG for SOC design verification with port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (5), 2001)

On automatic-verification pattern generation for SoC withport-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automatic interconnection rectification technique for SoC design integration. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ASP-DAC, 2003)

SoC design integration by using automatic interconnection rectification. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (4), 2003)

Automatic interconnection rectification for SoC design verification based on the port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. - Chen-Ling Chou; Chun-Yao Wang; Geeng-Wei Lee; Jing-Yang Jou (ICCD, 2004)

Verification on Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou; Chun-Yao Wang (ITC, 2004)

Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans. - Daniel J. Buehrer; Chun-Yao Wang (Web Intelligence, 2004)

An Improved Approach for AlternativeWires Identi.cation. - Yung-Chih Chen; Chun-Yao Wang (ICCD, 2005)

High level equivalence symmetric input identification. - Ming-Hong Su; Chun-Yao Wang (ASP-DAC, 2006)

The Potential and Limitation of Probability-Based Combinational Equivalence Checking. - Shih-Chieh Wu; Chun-Yao Wang; Jan-an Hsieh (ATS, 2006)

Language-Based High Level Transaction Extraction on On-chip Buses. - Yi-Le Huang; Chun-Yao Wang; Richard Yeh; Shih-Chieh Chang; Yung-Chih Chen (ISQED, 2006)

PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking. - Shih-Chieh Wu; Chun-Yao Wang (VLSI-SoC, 2006)

Recognition of Fanout-free Functions. - Tsung-Lin Lee; Chun-Yao Wang (ASP-DAC, 2007)

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. - Yu-Min Kuo; Cheng-Hung Lin; Chun-Yao Wang; Shih-Chieh Chang; Pei-Hsin Ho (ISQED, 2007)

A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. - Wen-Wen Hsieh; Po-Yuan Chen; Chun-Yao Wang; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol. - Chun-Yao Wang; Daniel J. Buehrer (IAT, 2008)

A Statistic-Based Approach to Testability Analysis. - Chuang-Chi Chiou; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2008)

Verification of Pin-Accurate Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Chun-Yao Wang; Jing-Yang Jou (IEEE Des. Test Comput., 2008)

Synthesis of reversible sequential elements. - Min-Lun Chuang; Chun-Yao Wang (ACM J. Emerg. Technol. Comput. Syst., 2008)

An Implicit Approach to Minimizing Range-Equivalent Circuits. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Novel Probabilistic Combinational Equivalence Checking. - Shih-Chieh Wu; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Dependent latch identification in the reachable state space. - Chen-Hsuan Lin 001; Chun-Yao Wang (ASP-DAC, 2009)

Rewiring using IRredundancy Removal and Addition. - Chun-Chi Lin; Chun-Yao Wang (DATE, 2009)

Enhancing SAT-based sequential depth computation by pruning search space. - Yung-Chih Chen; Chun-Yao Wang (ACM Great Lakes Symposium on VLSI, 2009)

Fast detection of node mergers using logic implications. - Yung-Chih Chen; Chun-Yao Wang (ICCAD, 2009)

An efficient approach to sip design integration. - Meng-Syue Chan; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2009)

A novel ACO-based pattern generation for peak power estimation in VLSI circuits. - Yi-Ling Liu; Chun-Yao Wang; Yung-Chih Chen; Ya-Hsin Chang (ISQED, 2009)

Dependent-Latch Identification in Reachable State Space. - Chen-Hsuan Lin 001; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Node addition and removal in the presence of don't cares. - Yung-Chih Chen; Chun-Yao Wang (DAC, 2010)

Distributed Transactions for Semantic Web Workflows - Overcoming the CAP Limitations on Virtual Organizations. - Daniel J. Buehrer; Chun-Yao Wang (ISPA, 2010)

The Cadabia Cloud. - Daniel J. Buehrer; Chun-Yao Wang; Li-Ren Chien (ISPA, 2010)

Fast Node Merging With Don't Cares Using Logic Implications. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Automated mapping for reconfigurable single-electron transistor arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (DAC, 2011)

On rewiring and simplification for canonicity in threshold logic circuits. - Pin-Yi Kuo; Chun-Yao Wang; Ching-Yi Huang (ICCAD, 2011)

A register-transfer level testability analyzer. - Yen-An Chen; Chun-Yao Wang; Ching-Yi Huang; Hsiu-Yi Lin (SoCC, 2011)

A probabilistic analysis method for functional qualification under Mutation Analysis. - Hsiu-Yi Lin; Chun-Yao Wang; Shih-Chieh Chang; Yung-Chih Chen; Hsuan-Ming Chou; Ching-Yi Huang; Yen-Chi Yang; Chun-Chien Shen (DATE, 2012)

CA-ABAC: Class Algebra Attribute-Based Access Control. - Daniel J. Buehrer; Chun-Yao Wang (Web Intelligence/IAT Workshops, 2012)

Gait analysis for patients with Alzheimer'S disease using a triaxial accelerometer. - Pau-Choo Chung; Yu-Liang Hsu; Chun-Yao Wang; Chien-Wen Lin; Jeen-Shing Wang; Ming-Chyi Pai (ISCAS, 2012)

Error Injection & Correction: An efficient formal logic restructuring algorithm. - Ching-Yi Huang; Daw-Ming Lee; Chun-Chi Lin; Chun-Yao Wang (ISOCC, 2012)

Deco: A Decentralized, Cooperative Atomic Commit Protocol. - Daniel J. Buehrer; Chun-Yao Wang (J. Comput. Networks Commun., 2012)

Logic Restructuring Using Node Addition and Removal. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On reconfigurable single-electron transistor arrays synthesis using reordering techniques. - Chang-En Chiang; Li-Fu Tang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2013)

Sensitization criterion for threshold logic circuits and its application. - Chen-Kuan Tsai; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ICCAD, 2013)

Pattern generation for Mutation Analysis using Genetic Algorithms. - Yen-Chi Yang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ISCAS, 2013)

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (ACM J. Emerg. Technol. Comput. Syst., 2013)

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. - Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Rewiring for threshold logic circuit minimization. - Chia-Chun Lin; Chun-Yao Wang; Yung-Chih Chen; Ching-Yi Huang (DATE, 2014)

Width minimization in the Single-Electron Transistor array synthesis. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2014)

BDD-based synthesis of reconfigurable single-electron transistor arrays. - Zheng Zhao; Chian-Wei Liu; Chun-Yao Wang; Weikang Qian (ICCAD, 2014)

Alzheimer's disease classification based on gait information. - Wei-Hsin Wang; Yu-Liang Hsu; Ming-Chyi Pai; Cheng-Hsiung Wang; Chun-Yao Wang; Chien-Wen Lin; Hao-Li Wu; Pau-Choo Chung (IJCNN, 2014)

Gait and Balance Analysis for Patients With Alzheimer's Disease Using an Inertial-Sensor-Based Wearable Instrument. - Yu-Liang Hsu; Pau-Choo Chung; Wei-Hsin Wang; Ming-Chyi Pai; Chun-Yao Wang; Chien-Wen Lin; Hao-Li Wu; Jeen-Shing Wang (IEEE J. Biomed. Health Informatics, 2014)

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. - Ching-Yi Huang; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (ASP-DAC, 2015)

Using structural relations for checking combinationality of cyclic circuits. - Wan-Chen Weng; Yung-Chih Chen; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang (DATE, 2015)

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. - Chen-Hsuan Lin 001; Subhendu Roy; Chun-Yao Wang; David Z. Pan; Deming Chen (ICCD, 2015)

Synthesis and verification of cyclic combinational circuits. - Jui-Hung Chen; Yung-Chih Chen; Wan-Chen Weng; Ching-Yi Huang; Chun-Yao Wang (SoCC, 2015)

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. - Ching-Yi Huang; Zheng-Shan Yu; Yung-Chun Hu; Tung-Chen Tsou; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Synthesis for Width Minimization in the Single-Electron Transistor Array. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2015)

MajorSat: A SAT solver to majority logic. - Yu-Min Chou; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (ASP-DAC, 2016)

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. - Tai-Lin Chen; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (J. Multiple Valued Log. Soft Comput., 2016)

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. - Chen-Yu Lin; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu (IEEE Trans. Multi Scale Comput. Syst., 2016)

Area-Aware Decomposition for Single-Electron Transistor Arrays. - Ching-Hsuan Ho; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Suman Datta; Vijaykrishnan Narayanan (ACM Trans. Design Autom. Electr. Syst., 2016)

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. - Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Majority logic circuits optimisation by node merging. - Chun-Che Chung; Yung-Chih Chen; Chun-Yao Wang; Chia-Cheng Wu (ASP-DAC, 2017)

In&Out: Restructuring for threshold logic network optimization. - Chia-Chun Lin; Chiao-Wei Huang; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2017)

A case study on mathematical expression recognition to GPU. - Ying-Chin Lin; Chun-Yao Wang; Jing-Yun Zeng (J. Supercomput., 2017)

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. - Yun-Jui Li; Ching-Yi Huang; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. - Yung-An Lai; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

Logic optimization with considering boolean relations. - Tung-Yuan Lee; Chia-Cheng Wu; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. - Chia-Cheng Wu; Tung-Yuan Lee; Yung-An Lai; Hsin-Pei Wang; De-Xuan Ji; Yan-Ping Chang; Teng-Chia Wang; Chin-Heng Liu; Chun-Yao Wang; Yung-Chih Chen (ACM Great Lakes Symposium on VLSI, 2018)

Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. - Chia-Cheng Wu; Kung-Han Ho; Juinn-Dar Huang; Chun-Yao Wang (ISVLSI, 2018)

Using range-equivalent circuits for facilitating bounded sequential equivalence checking. - Yung-Chih Chen; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang (VLSI-DAT, 2018)

On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. - Hsin-Pei Wang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. - Yan-Ping Chang; Teng-Chia Wang; Yun-Ju Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

A Glitch Key-Gate for Logic Locking. - De-Xuan Ji; Hsiao-Yu Chiang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. - Chin-Heng Liu; Chia-Chun Lin; Yung-Chih Chen; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Convolutional Result Sharing Approach for Binarized Neural Network Inference. - Ya-Chun Chang; Chia-Chun Lin; Yi-Ting Lin; Yung-Chih Chen; Chun-Yao Wang (DATE, 2020)

Rehabilitation System for Limbs using IMUs. - Chun-Jui Chen; Yi-Ting Lin; Chia-Chun Lin; Yung-Chih Chen; Yun-Ju Lee; Chun-Yao Wang (ISQED, 2020)

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement. - Teng-Chia Wang; Yan-Ping Chang; Chun-Jui Chen; Yun-Ju Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2020)

A Dynamic Expansion Order Algorithm for the SAT-based Minimization. - Chia-Chun Lin; Kit Seng Tam; Chana-Cheng Ko; Hsin-Ping Yen; Shenz-Hsiu Wei; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2020)

LOOPLock: Logic Optimization-Based Cyclic Logic Locking. - Hsiao-Yu Chiang; Yung-Chih Chen; De-Xuan Ji; Xiang-Min Yang; Chia-Chun Lin; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A New Necessary Condition for Threshold Function Identification. - Chia-Chun Lin; Chin-Heng Liu; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A General Equivalence Checking Framework for Multivalued Logic. - Chia-Chun Lin; Hsin-Ping Yen; Sheng-Hsiu Wei; Pei-Pei Chen; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2021)

An Efficient Approximate Node Merging with an Error Rate Guarantee. - Kit Seng Tam; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2021)

Overview of 2021 CAD Contest at ICCAD. - Tsung-Wei Huang; Yu-Guang Chen; Chun-Yao Wang; Takashi Sato 001 (ICCAD, 2021)

On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. - Hsin-Tsung Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2021)

On Reduction of Computations for Threshold Function Identification. - Wen-Chih Hsu; Chia-Chun Lin; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

Cluster Tool Performance Analysis using Graph Database. - Shiuan-Hau Huang; Hsin-Ping Yen; Yan-Hsiu Liu; Kuang-Hsien Tseng; Ji-Fu Kung; Chia-Chun Lin; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

An IMU-aided Fitness System. - Yi-Ting Lin; Chun-Jui Chen; Pei-Yi Kuo; Si-Huei Lee; Chia-Chun Lin; Yun-Ju Lee; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

Industry 3.5 to empower smart production for poultry farming and an empirical study for broiler live weight prediction. - Chun-Yao Wang; Ying-Jen Chen; Chen-Fu Chien 001 (Comput. Ind. Eng., 2021)

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. - Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Yung-Chih Chen; Juinn-Dar Huang; Chun-Yao Wang (ACM J. Emerg. Technol. Comput. Syst., 2021)

Overview of 2022 CAD Contest at ICCAD. - Yu-Guang Chen; Chun-Yao Wang; Tsung-Wei Huang; Takashi Sato 001 (ICCAD, 2022)

An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. - Pei-Pei Chen; Xiang-Min Yang; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ICCAD, 2022)

Majority Logic Circuit Minimization Using Node Addition and Removal. - Chang-Cheng Ko; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. - Chia-Chun Lin; Ciao-Syun Lin; You-Hsuen Tsai; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks. - Hsiao-Lun Liu; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. - Xiang-Min Yang; Pei-Pei Chen; Hsiao-Yu Chiang; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. - Chun-Ting Lee; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2023)

A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. - Hsiao-Lun Liu; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2023)

Invited Paper: Overview of 2023 CAD Contest at ICCAD. - Takashi Sato 001; Chun-Yao Wang; Yu-Guang Chen; Tsung-Wei Huang (ICCAD, 2023)

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation. - Hsin-Ping Yen; Shiuan-Hau Huang; Yan-Hsiu Liu; Kuang-Hsien Tseng; Ji-Fu Kung; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2023)

A Constructive Approach for Threshold Function Identification. - Meng-Jing Li; Yu-Chuan Yen; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ACM Trans. Design Autom. Electr. Syst., 2023)

LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. - Pei-Pei Chen; Xiang-Min Yang; Yu-Cheng He; Yung-Chih Chen; Yi-Ting Li; Chun-Yao Wang (ASPDAC, 2024)

A Hybrid Approach to Reverse Engineering on Combinational Circuits. - Wuqian Tang; Yi-Ting Li; Kai-Po Hsu; Kuan-Ling Chou; You-Cheng Lin; Chia-Feng Chien; Tzu-Li Hsu; Yung-Chih Chen; Ting-Chi Wang; Shih-Chieh Chang; TingTing Hwang; Chun-Yao Wang (DATE, 2024)

IR drop Prediction Based on Machine Learning and Pattern Reduction. - Yong-Fong Chang; Yung-Chih Chen; Yu-Chen Cheng; Shu-Hong Lin; Che-Hsu Lin; Chun-Yuan Chen; Yu-Hsuan Chen; Yu-Che Lee; Jia-Wei Lin; Hsun-Wei Pao; Shih-Chieh Chang; Yi-Ting Li; et al. (ACM Great Lakes Symposium on VLSI, 2024)

On Construction of Trajectory of Boxer's Punch using a single IMU. - Yu-Cheng Lee; Kai-Po Hsu; Yun-Ju Lee; Yi-Ting Li; Wuqian Tang; Yung-Chih Chen; Wen-Hsin Chiu; Chun-Yao Wang (ISPACS, 2024)

Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. - Wuqian Tang; Chuan-Shun Huang; Yung-Chih Chen; Yi-Ting Li; Shih-Chieh Chang; Chun-Yao Wang (SOCC, 2024)

9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function. - Yu-Chuan Yen; Meng-Jing Li; Yi-Ting Li; Yung-Chih Chen; Ihao Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. - Yu-Hsuan Chen; Yu-Chen Cheng; Yong-Fong Chang; Yu-Che Lee; Jia-Wei Lin; Hsun-Wei Pao; Peng-Wen Chen; Po-Yu Chen; Hao-Yun Chen; Yung-Chih Chen; Chun-Yao Wang; Shih-Chieh Chang (DATE, 2025)

CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation. - Kuan-Ling Chou; Cheng-Lung Wang; Yung-Chih Chen; Wuqian Tang; Yi-Ting Li; Shih-Chieh Chang; Chun-Yao Wang (ACM Great Lakes Symposium on VLSI, 2025)

IMU-Based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform. - Kai-Po Hsu; Tsung-Han Lai; Yi-Ting Li; Wuqian Tang; Yun-Ju Lee; Yung-Chih Chen; Wen-Hsin Chiu; Chun-Yao Wang (ISQED, 2025)