BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. - Chun-Yeh Liu; Kewal K. Saluja; Shambhu J. Upadhyaya (DAC, 1987)

An efficient algorithm for bipartite PLA folding. - Chun-Yeh Liu; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

An optimized testable architecture for finite state machines. - Ting-Yu Kuo; Chun-Yeh Liu; Kewal K. Saluja (VTS, 1995)