ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR. - Ming-Dou Ker; Chun-Yu Lin 001; Guo-Xuan Meng (ISCAS, 2008)

Low-Capacitance and Fast Turn-on SCR for RF ESD Protection. - Chun-Yu Lin 001; Ming-Dou Ker; Guo-Xuan Meng (IEICE Trans. Electron., 2008)

2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process. - Chun-Yu Lin 001; Ming-Dou Ker (ISCAS, 2010)

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme. - Chun-Yu Lin 001; Ming-Dou Ker; Yuan-Wen Hsiao (Microelectron. Reliab., 2010)

Modified LC-tank ESD protection design for 60-GHz RF applications. - Chun-Yu Lin 001; Li-Wei Chu; Shiang-Yu Tsai; Ming-Dou Ker; Tse-Hua Lu; Tsun-Lai Hsu; Ping-Fang Hung; Ming-Hsiang Song; Jeng-Chou Tseng; Tzu-Heng Chang; Ming-Hsien Tsai 002 (ECCTD, 2011)

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process. - Chun-Yu Lin 001; Li-Wei Chu; Ming-Dou Ker (Microelectron. Reliab., 2011)

Design of ESD protection for RF CMOS power amplifier with inductor in matching network. - Shiang-Yu Tsai; Chun-Yu Lin 001; Li-Wei Chu; Ming-Dou Ker (APCCAS, 2012)

Design of negative high voltage generator for biphasic stimulator with soc integration consideration. - Ya-Chun Huang; Ming-Dou Ker; Chun-Yu Lin 001 (BioCAS, 2012)

Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability. - Ming-Dou Ker; Wei-Ling Chen; Chun-Yu Lin 001 (BioCAS, 2012)

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology. - Li-Wei Chu; Chun-Yu Lin 001; Shiang-Yu Tsai; Ming-Dou Ker; Ming-Hsiang Song; Chewnpu Jou; Tse-Hua Lu; Jeng-Chou Tseng; Ming-Hsien Tsai 002; Tsun-Lai Hsu; Ping-Fang Hung; Tzu-Heng Chang (ISCAS, 2012)

An improved wavelet-tree watermarking scheme. - Chun-Yu Lin 001; Chung-Yen Su (ISPACS, 2012)

High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process. - Chun-Yu Lin 001; Yi-Ju Li; Ming-Dou Ker (NEWCAS, 2012)

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process. - Chun-Yu Lin 001; Tang-Long Chang; Ming-Dou Ker (Microelectron. Reliab., 2012)

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Shun-Ting Chang; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; et al. (ISSCC, 2013)

Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability. - Chun-Yu Lin 001; Wei-Ling Chen; Ming-Dou Ker (IEEE Trans. Biomed. Circuits Syst., 2013)

On-chip ESD protection designs with SCR-based devices in RF integrated circuits. - Chun-Yu Lin 001; Rong-Kun Chang (ICCE-TW, 2014)

ESD protection design for wideband RF applications in 65-nm CMOS process. - Li-Wei Chu; Chun-Yu Lin 001; Ming-Dou Ker; Ming-Hsiang Song; Jeng-Chou Tseng; Chewnpu Jou; Ming-Hsien Tsai 002 (ISCAS, 2014)

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant. - Kuan-Yu Lin; Ming-Dou Ker; Chun-Yu Lin 001 (ISCAS, 2014)

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control. - Wei-Ming Chen; Herming Chiueh; Tsan-Jieh Chen; Chia-Lun Ho; Chi Jeng; Ming-Dou Ker; Chun-Yu Lin 001; Ya-Chun Huang; Chia-Wei Chou; Tsun-Yuan Fan; Ming-Seng Cheng; Yue-Loong Hsin; et al. (IEEE J. Solid State Circuits, 2014)

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process. - Chun-Yu Lin 001; Yan-Lian Chiu (Microelectron. Reliab., 2015)

On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance consideration. - Guan-Yi Li; Chun-Yu Lin 001 (APCCAS, 2016)

ESD protection design for high-speed circuits in nanoscale CMOS process. - Chun-Yu Lin 001; Rong-Kun Chang (ISIC, 2016)

ESD protection design for high-speed applications in CMOS technology. - Jie-Ting Chen; Chun-Yu Lin 001; Rong-Kun Chang; Ming-Dou Ker; Tzu-Chien Tzeng; Tzu-Chiang Lin (MWSCAS, 2016)

Design of local ESD clamp for cross-power-domain interface circuits. - Chun-Yu Lin 001; Yu-Kai Chiu; Shuan-Yu Yueh (IEICE Electron. Express, 2016)

Improved stacked-diode ESD protection in nanoscale CMOS technology. - Chun-Yu Lin 001; Meng-Ting Lin (IEICE Electron. Express, 2017)

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process. - Chun-Yu Lin 001; Rui-Hong Liu; Ming-Dou Ker (Microelectron. Reliab., 2017)

Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology. - Guo-Lun Huang; Wei-Hao Fu; Chun-Yu Lin 001 (Microelectron. Reliab., 2018)

Low-Loss I/O Pad With ESD Protection for K/Ka-Bands Applications in the Nanoscale CMOS Process. - Bo-Wei Peng; Chun-Yu Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Bidirectional ESD Protection Circuit With High Reliability and Low Leakage for Consumer Electronic Products. - Chun-Cheng Chen; Chun-Yu Lin 001 (ICCE-Taiwan, 2024)

Study of Silicide Blocking for GGNMOS Performance and Turn-On Time in CMOS Process. - Er-Wen Chien; Hao-En Cheng; Chun-Yu Lin 001 (ICCE-Taiwan, 2024)