A New algorithm for combined PLA folding. - Chunduri Rama Mohan; Partha Pratim Chakrabarti; Sujoy Ghose (VLSI Design, 1992)

Combining State Assignment with PLA Folding. - Chunduri Rama Mohan; Partha Pratim Chakrabarti; Sujoy Ghose (VLSI Design, 1993)

A new approach for factorizing FSM's. - Chunduri Rama Mohan; Partha Pratim Chakrabarti (ICCAD, 1994)

A New Approach to Synthesis of PLA-Based FSM's. - Chunduri Rama Mohan; Partha Pratim Chakrabarti (VLSI Design, 1994)

Combined optimization of area and testability during state assignment of PLA-based FSM's. - Chunduri Rama Mohan; Partha Pratim Chakrabarti (VLSI Design, 1995)

EARTH: combined state assignment of PLA-based FSM's targeting area and testability. - Chunduri Rama Mohan; Partha Pratim Chakrabarti (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. - Chunduri Rama Mohan; Srobona Mitra; Partha Pal Chaudhuri (VLSI Design, 1997)

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? - Prasenjit Basu; Sayantan Das 001; Pallab Dasgupta; P. P. Chakrabarti 001; Chunduri Rama Mohan; Limor Fix (DATE, 2004)

Formal verification coverage: computing the coverage gap between temporal specifications. - Sayantan Das 001; Prasenjit Basu; Ansuman Banerjee; Pallab Dasgupta; P. P. Chakrabarti 001; Chunduri Rama Mohan; Limor Fix; Roy Armoni (ICCAD, 2004)

Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. - Prasenjit Basu; Pallab Dasgupta; P. P. Chakrabarti 001; Chunduri Rama Mohan (VLSI Design, 2004)

Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. - Sayantan Das 001; Ansuman Banerjee; Prasenjit Basu; Pallab Dasgupta; P. P. Chakrabarti 001; Chunduri Rama Mohan; Limor Fix (VLSI Design, 2005)

Design-Intent Coverage - A New Paradigm for Formal Property Verification. - Prasenjit Basu; Sayantan Das 001; Ansuman Banerjee; Pallab Dasgupta; P. P. Chakrabarti 001; Chunduri Rama Mohan; Limor Fix; Roy Armoni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

An ECO Technique for Removing Crosstalk Violations in Clock Networks. - Amit Kumar 004; Krishnendu Chakrabarty; Chunduri Rama Mohan (VLSI Design, 2007)

Cohesive Coverage Management for Simulation and Formal Property Verification. - Aritra Hazra; Ansuman Banerjee; Srobona Mitra; Pallab Dasgupta; Partha Pratim Chakrabarti; Chunduri Rama Mohan (ISVLSI, 2008)

Formal Verification of Power Management Logic with Mixed-Signal Domains. - Sudipa Mandal; Antonio Anastasio Bruto da Costa; Aritra Hazra; Pallab Dasgupta; Bhushan Naware; Chunduri Rama Mohan; Sanjib Basu (VLSID, 2017)

Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components. - Sudipa Mandal; Aritra Hazra; Pallab Dasgupta; Chunduri Rama Mohan (VLSID, 2018)

Assertions for Protecting Mixed-Signal Latency Contracts in Power Management. - Sudipa Mandal; Pallab Dasgupta; Aritra Hazra; Chunduri Rama Mohan (IEEE Trans. Very Large Scale Integr. Syst., 2020)