Adaptive postprocessors with DCT-based block classifications. - Chung-Bin Wu; Bin-Da Liu; Jar-Ferr Yang (IEEE Trans. Circuits Syst. Video Technol., 2003)

A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers. - Chung-Bin Wu; Bin-Da Liu; Jar-Ferr Yang (IEEE Trans. Instrum. Meas., 2003)

DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. - Chung-Bin Wu; Chin-Yuan Yao; Bin-Da Liu; Jar-Ferr Yang (IEEE Trans. Circuits Syst. Video Technol., 2005)

An efficient background extraction and object segmentation algorithm for realtime applications. - Hsin-Yi Wang; Li-Hung Wang; Chung-Bin Wu (APCCAS, 2012)

A hardware sharing architecture of deblocking filter for VP8 and H.264/AVC video coding. - Yu-Lin Chou; Chung-Bin Wu (ISCAS, 2012)

A real-time architecture of multiple features extraction for vehicle verification. - Li-Hung Wang; Chao-Kai Cheng; Chung-Bin Wu (APCCAS, 2014)

Object-based stereo matching using adjustable-cross for depth estimation. - Li-Hung Wang; Kai-Lung Tsai; Chung-Bin Wu (ICCE-TW, 2015)

A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC. - Chia-Wei Chang; Hao-Fan Hsu; Chih-Peng Fan; Chung-Bin Wu; Robert Chen-Hao Chang (J. Signal Process. Syst., 2016)

Hardware-and-memory-sharing architecture of deblocking filter for VP8 and H.264/AVC. - Chung-Bin Wu; Li-Hung Wang; Yu-Lin Chou (IEEE Trans. Consumer Electron., 2017)

High Throughput Hardware Implementation for Deep Learning AI Accelerator. - Chung-Bin Wu; Yu-Cheng Hsueh; Ching-Shun Wang; Yen-Chi Lai (ICCE-TW, 2019)

Low Complexity License Plate Recognition System. - Chung-Bin Wu; Guan-Jing Chen; Chien-Cheng Yu (ISOCC, 2019)

Ultra-Low Complexity Block-Based Lane Detection and Departure Warning System. - Chung-Bin Wu; Li-Hung Wang; Kuan-Chieh Wang (IEEE Trans. Circuits Syst. Video Technol., 2019)

Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator. - Chung-Bin Wu; Ching-Shun Wang; Yu-Kuan Hsiao (GCCE, 2020)

Cordic Based Hardware Implementation for Object Region Layer of Yolo V2. - Chung-Bin Wu; Yu-Kuan Hsiao (ICCE-TW, 2020)

High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator. - Chung-Bin Wu; Yin-Tsung Hwang; Yu-Cheng Hsueh; Yu-Kuan Hsiao (ISOCC, 2020)

iAMEC, an Intelligent Autonomous Mover for Navigation in Indoor People Rich Environments. - Yin-Tsung Hwang; Kuan-Hong Chen; Chih-Peng Fan; Yong-Kang Lai; Chung-Bin Wu; Hsiao-Ping Tsai; Wei-Liang Lin; Kuang-Hao Lin (AICAS, 2021)

Reconfigurable Deep Learning Accelerator Hardware Architecture Design for Sparse CNN. - Chung-Bin Wu; Chung-Hsuan Chen; Chen-Peng Kuan (ICCE-TW, 2021)

Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator. - Chung-Bin Wu; Yu-Kuan Hsiao; Wei-Hsuan Chang (AICAS, 2022)

Quantized Lite Convolutional Neural Network Hardware Accelerator Design with FPGA for Face Direction Recognition. - Ko-Yi Jiang; Hsing-Yao Wang; Chung-Bin Wu; Yin-Tsung Hwang; Chih-Peng Fan (ICCE-TW, 2022)

Hetero Layer Fusion Based Architecture Design and Implementation for of Deep Learning Accelerator. - Chung-Bin Wu; Rui-Feng Wu; Tzu-Wei Chan (ICCE-TW, 2022)

AI Crowd Control Detection System Implemented on FPGA Hardware Development Platform. - Chung-Bin Wu; Yu-Hu Wu; Yi-Yen Lai (ICCE, 2022)

Design and FPGA Implementation of Lite Convolutional Neural Network Based Hardware Accelerator for Ocular Biometrics Recognition Technology. - Wei-Che Sun; Chih-Peng Fan; Chung-Bin Wu (MCSoC, 2022)

System Integration and Optimization of AI Hardware Acceleration Architecture for Object Detection. - Chung-Bin Wu; Yi-Yen Lai; Yen-Ren Hou (ICCE-Taiwan, 2023)