A Fast-Convergence Decoding Method and Memory-Efficient VLSI Decoder Architecture for Irregular LDPC Codes in the IEEE 802.16e Standards. - Yeong-Luh Ueng; Chung-Chao Cheng (VTC Fall, 2007)

A study into high-throughput decoder architectures for high-rate LDPC codes. - Yeong-Luh Ueng; Chung-Chao Cheng (ISOCC, 2012)

An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes. - Yeong-Luh Ueng; Chen-Yap Leong; Chung-Jay Yang; Chung-Chao Cheng; Kuo-Hsuan Liao; Shu-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders. - Huang-Chang Lee; Chung-Chao Cheng; Yeong-Luh Ueng (ISTC, 2014)

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications. - Chung-Chao Cheng; Jeng-Da Yang; Huang-Chang Lee; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems. - Yan-Tong Chen; Wei-Cheng Sun; Chung-Chao Cheng; Tsung-Lin Tsai; Yeong-Luh Ueng; Chia-Hsiang Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)