Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. - Chung-Cheng Chou; Zheng-Jun Lin; Pei-Ling Tseng; Chih-Feng Li; Chih-Yang Chang; Wei-Chi Chen; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2018)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. - Tai-Hao Wen; Hung-Hsi Hsu; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (ISSCC, 2024)

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. - Hung-Hsi Hsu; Tai-Hao Wen; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Ashwin Sanjay Lele; Bo Zhang; Ping-Sheng Wu; et al. (IEEE J. Solid State Circuits, 2025)