An Adaptive Neural Spike Detector with Threshold-lock Loop. - Chung-Ching Peng; Pawan Sabharwal; Rizwan Bashirullah (ISCAS, 2009)

Toward Energy Efficient Neural Interfaces. - Chung-Ching Peng; Zhiming Xiao; Rizwan Bashirullah (IEEE Trans. Biomed. Eng., 2009)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization. - Chien-Pang Lu; Iris Hui-Ru Jiang; Chung-Ching Peng; Mohd Mawardi Mohd Razha; Alessandro Uber (ISPD, 2024)