A half-micron CMOS logic generation. - Charles W. Koburger III; William F. Clark; James W. Adkisson; Eric Adler; Paul E. Bakeman; Albert S. Bergendahl; Alan B. Botula; W. Chang; Bijan Davari; John H. Givens; Howard H. Hansen; Steven J. Holmes; et al. (IBM J. Res. Dev., 1995)

Ultralow-power SRAM technology. - Randy W. Mann; W. W. (Bill) Abadeer; Matthew J. Breitwisch; O. Bula; Jeff S. Brown; Bryant C. Colwill; Peter E. Cottrell; William T. Crocco Jr.; Stephen S. Furkay; Michael J. Hauser; Terence B. Hook; Dennis Hoyniak; et al. (IBM J. Res. Dev., 2003)

A novel CMOS compatible embedded nonvolatile memory with zero process adder. - Matthew J. Breitwisch; Chung Hon Lam; Jeffrey B. Johnson; Steven W. Mittl; Jian W. Zhu (MTDT, 2005)

Overview of candidate device technologies for storage-class memory. - Geoffrey W. Burr; Bülent N. Kurdi; J. Campbell Scott; Chung Hon Lam; Kailash Gopalakrishnan; Rohit S. Shenoy (IBM J. Res. Dev., 2008)

Transition-metal-oxide-based resistance-change memories. - Siegfried F. Karg; Gerhard Ingmar Meijer; J. Georg Bednorz; Charles T. Rettner; Alejandro G. Schrott; Eric A. Joseph; Chung Hon Lam; Markus Janousch; Urs Staub; Fabio LaMattina; Santos F. Alvarado; Daniel Widmer; et al. (IBM J. Res. Dev., 2008)

Phase-change random access memory: A scalable technology. - Simone Raoux; Geoffrey W. Burr; Matthew J. Breitwisch; Charles T. Rettner; Yi-Chou Chen; Robert M. Shelby; Martin Salinga; Daniel Krebs; Shih-Hung Chen; Hsiang-Lan Lung; Chung Hon Lam (IBM J. Res. Dev., 2008)

Multilevel phase-change memory. - Nikolaos Papandreou; Aggeliki Pantazi; Abu Sebastian; Matthew J. Breitwisch; Chung Hon Lam; Haralampos Pozidis; Evangelos Eleftheriou (ICECS, 2010)

Programming algorithms for multilevel phase-change memory. - Nikolaos Papandreou; Haralampos Pozidis; Aggeliki Pantazi; Abu Sebastian; Matthew J. Breitwisch; Chung Hon Lam; Evangelos Eleftheriou (ISCAS, 2011)

Nanoscale electronic synapses using phase change devices. - Bryan L. Jackson; Bipin Rajendran; Gregory S. Corrado; Matthew J. Breitwisch; Geoffrey W. Burr; Roger Cheek; Kailash Gopalakrishnan; Simone Raoux; Charles T. Rettner; Alvaro Padilla; Alejandro G. Schrott; Rohit S. Shenoy; et al. (ACM J. Emerg. Technol. Comput. Syst., 2013)

A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell. - Gael F. Close; Urs Frey; Jack Morrish; Richard Jordan; Scott C. Lewis; Tom Maffitt; M. J. BrightSky; Christoph Hagleitner; Chung Hon Lam; Evangelos Eleftheriou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Recent Progress in Phase-Change Memory Technology. - Geoffrey W. Burr; Matthew J. BrightSky; Abu Sebastian; Huai-Yu Cheng; Jau-Yi Wu; SangBum Kim; Norma E. Sosa; Nikolaos Papandreou; Hsiang-Lan Lung; Haralampos Pozidis; Evangelos Eleftheriou; Chung Hon Lam (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)