Hierarchical value cache encoding for off-chip data bus. - Chung-Hsiang Lin; Chia-Lin Yang; Ku-Jei King (ISLPED, 2006)

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. - Chung-Hsiang Lin; Chia-Lin Yang; Ku-Jei King (ISLPED, 2009)

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. - Ping-Hung Yuh; Chia-Lin Yang; Chi-Feng Li; Chung-Hsiang Lin (ACM Trans. Design Autom. Electr. Syst., 2009)

Memory Latency Reduction via Thread Throttling. - Hsiang-Yun Cheng; Chung-Hsiang Lin; Jian Li; Chia-Lin Yang (MICRO, 2010)

SECRET: Selective error correction for refresh energy reduction in DRAMs. - Chung-Hsiang Lin; De-Yu Shen; Yi-Jung Chen; Chia-Lin Yang; Cheng-Yuan Michael Wang (ICCD, 2012)

SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. - Chung-Hsiang Lin; De-Yu Shen; Yi-Jung Chen; Chia-Lin Yang; Cheng-Yuan Michael Wang (ACM Trans. Archit. Code Optim., 2015)

PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. - Chung-Hsiang Lin; Shao-Fu Lin; Yi-Jung Chen; En-Yu Jenp; Chia-Lin Yang (ASP-DAC, 2022)