A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)