VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. - Yeong-Luh Ueng; Chung-Jay Yang; Zong-Cheng Wu; Chen-Eng Wu; Yu-Lun Wang (ISCAS, 2008)

A Shuffled Message-passing Decoding Method for Memory-based LDPC Decoders. - Yeong-Luh Ueng; Chung-Jay Yang; Chun-Jung Chen (ISCAS, 2009)

A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes. - Yeong-Luh Ueng; Chung-Jay Yang; Kuan-Chieh Wang; Chun-Jung Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A selective-input non-binary LDPC decoder architecture. - Yeong-Luh Ueng; Chung-Jay Yang; Shu-Wei Chen; Wei-Xuan Wu (ISOCC, 2011)

Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec. - Yu-Luen Wang; Yeong-Luh Ueng; Chien-Lien Peng; Chung-Jay Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes. - Yeong-Luh Ueng; Chen-Yap Leong; Chung-Jay Yang; Chung-Chao Cheng; Kuo-Hsuan Liao; Shu-Wei Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture. - Yeong-Luh Ueng; Yu-Luen Wang; Li-Sheng Kan; Chung-Jay Yang; Yung-Hsiang Su (IEEE Trans. Signal Process., 2012)

An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding. - Yeong-Luh Ueng; Bo-Jhang Yang; Chung-Jay Yang; Huang-Chang Lee; Jeng-Da Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA. - Yeong-Luh Ueng; Kuo-Hsuan Liao; Hsueh-Chih Chou; Chung-Jay Yang (IEEE Trans. Signal Process., 2013)