Compiler Supports and Optimizations for PAC VLIW DSP Processors. - Yung-Chia Lin; Chung-Lin Tang; Chung-Ju Wu; Ming-Yu Hung; Yi-Ping You; Ya-Chiao Moo; Sheng-Yuan Chen; Jenq Kuen Lee (LCPC, 2005)

Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files. - Chung-Ju Wu; Sheng-Yuan Chen; Jenq Kuen Lee (LCPC, 2006)

Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. - Chi Wu; Kun-Yuan Hsieh; Yung-Chia Lin; Chung-Ju Wu; Wen-Li Shih; Shih-Chang Chen; Chung-Kai Chen; Chien-Ching Huang; Yi-Ping You; Jenq Kuen Lee (RTCSA, 2006)

Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. - Yung-Chia Lin; Chia-Han Lu; Chung-Ju Wu; Chung-Lin Tang; Yi-Ping You; Ya-Chiao Moo; Jenq Kuen Lee (J. Signal Process. Syst., 2008)

Programming model and tools for embedded multicore systems. - Chung-Wen Huang; Wen-Li Shih; Chung-Ju Wu; Jia-Jhe Li; Jenq Kuen Lee (Int. J. Embed. Syst., 2010)

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. - David Chih-Wei Chang; Tay-Jyi Lin; Chung-Ju Wu; Jenq Kuen Lee; Yuan-Hua Chu; An-Yeu Wu (J. Signal Process. Syst., 2011)

Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files. - Chung-Ju Wu; Yu-Te Lin; Jenq Kuen Lee (J. Supercomput., 2012)

Register spilling via transformed interference equations for PAC DSP architecture. - Chung-Ju Wu; Chia-Han Lu; Jenq Kuen Lee (Concurr. Comput. Pract. Exp., 2014)

Achieving spilling-friendly register file assignment for highly distributed register files. - Chia-Han Lu; Wen-Li Shih; Chung-Ju Wu; Jenq Kuen Lee (J. Supercomput., 2014)