A Parallel Pattern Mixed-Level Fault Simulator. - Tyh-Song Hwang; Chung Len Lee 001; Wen-Zen Shen; Ching Ping Wu (DAC, 1990)

Checkpoints in irredundant two-level combinational circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (J. Electron. Test., 1991)

Single-fault fault-collapsing analysis in sequential logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. - Ching Ping Wu; Chung Len Lee 001; Wen-Zen Shen (EURO-DAC, 1992)

Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1992)

MT-SIM a mixed-level transition fault simulator based on parallel patterns. - Chung Len Lee 001; Ching Ping Wu; Wen-Zen Shen; Tyh-Song Hwang; Shueng Dar Hwang (J. Electron. Test., 1992)

TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. - Meng Chiy Lin; Jwu E. Chen; Chung-Len Lee 001 (EDAC-ETC-EUROASIC, 1994)

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen; Won Yih Lin (EDAC-ETC-EUROASIC, 1994)

Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

Complete Test Set for Multiple-Valued Logic Networks. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1994)

Simplifying Sequential Circuit Test Generation. - Meng-Lieh Sheu; Chung-Len Lee 001 (IEEE Des. Test Comput., 1994)

A complement-based fast algorithm to generate universal test sets for multi-output functions. - Beyin Chen; Chung-Len Lee 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Fanout fault analysis for digital logic circuits. - Jwu E. Chen; Chung-Len Lee 001; Wen-Zen Shen; Beyin Chen (Asian Test Symposium, 1995)

A programmable multiple-sequence generator for BIST applications. - Meng-Lieh Sheu; Chung-Len Lee 001 (Asian Test Symposium, 1995)

Identification of robust untestable path delay faults. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1995)

Factorization of Multi-Valued Logic Functions. - Hui Min Wang; Chung-Len Lee 001; Jwu E. Chen (ISMVL, 1995)

Identifying Untestable Faults in Sequential Circuits. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Des. Test Comput., 1995)

Universal test set generation for CMOS circuits. - Beyin Chen; Chung-Len Lee 001 (J. Electron. Test., 1995)

Invalid State Identification for Sequential Circuit Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 1996)

A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines. - Chung-Len Lee 001; Meng-Lieh Sheu (IEEE Trans. Computers, 1996)

Fault diagnosis of odd-even sorting networks. - Chih Wei Hu; Chung-Len Lee 001; Wen Ching Wu; Jwu E. Chen (Asian Test Symposium, 1997)

Functional test pattern generation for CMOS operational amplifier. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1997)

Identifying invalid states for sequential circuit test generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Maximization of power dissipation under random excitation for burn-in testing. - Kuo-Chan Huang; Chung-Len Lee 001; Jwu E. Chen (ITC, 1998)

Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. - Hsing-Chung Liang; Chung-Len Lee 001; Jwu E. Chen (VTS, 1998)

A Two-Phase Fault Simulation Scheme for Sequential Circuits. - Wen Ching Wu; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 1998)

Analog Metrology and Stimulus Selection in a Noisy Environment. - Chauchin Su; Yue-Tsang Chen; Chung-Len Lee 001 (Asian Test Symposium, 1999)

A DFT for semi-DC fault diagnosis for switched-capacitor circuits. - Sheng-Jer Kuo; Chung Len Lee 001; Soon-Jyh Chang; Jwu E. Chen (ETW, 1999)

A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. - Kuo-Chan Huang; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 1999)

A methodology for fault model development for hierarchical linear systems. - Yin-Chao Huang; Chung-Len Lee 001; Jun-Weir Lin; Jwu E. Chen; Chauchin Su (Asian Test Symposium, 2000)

Is IDDQ testing not applicable for deep submicron VLSI in year 2011? - Chih-Wen Lu; Chauchin Su; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2000)

All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. - Chauchin Su; Yue-Tsang Chen; Mu-Jeng Huang; Gen-Nan Chen; Chung-Len Lee 001 (DATE, 2000)

Oscillation Ring Delay Test for High Performance Microprocessors. - Wen Ching Wu; Chung-Len Lee 001; Ming Shae Wu; Jwu E. Chen; Magdy S. Abadir (J. Electron. Test., 2000)

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. - Yeong-Jar Chang; Chung-Len Lee 001; Jwu E. Chen; Chauchin Su (J. Inf. Sci. Eng., 2000)

A computer aided engineering system for memory BIST. - Chauchin Su; Shih-Ching Hsiao; Hau-Zen Zhau; Chung-Len Lee 001 (ASP-DAC, 2001)

Fault Diagnosis for Linear Analog Circuits. - Jun-Weir Lin; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2001)

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. - Ming Shae Wu; Chung-Len Lee 001; Chi Peng Chang; Jwu E. Chen (Asian Test Symposium, 2002)

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. - Jun-Weir Lin; Chung-Len Lee 001; Jwu E. Chen (DATE, 2002)

A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. - Chih-Wen Lu; Chung-Len Lee 001 (DELTA, 2002)

Structural Fault Based Specification Reduction for Testing Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Electron. Test., 2002)

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. - Chih-Wen Lu; Chung-Len Lee 001; Chauchin Su; Jwu-E Chen (J. Electron. Test., 2002)

A low-power high-speed class-AB buffer amplifier for flat-panel-display application. - Chih-Wen Lu; Chung-Len Lee 001 (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. - Soon-Jyh Chang; Chung-Len Lee 001; Jwu E. Chen (J. Inf. Sci. Eng., 2003)

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. - Guan-Xun Chen; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2004)

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2004)

Oscillation ring based interconnect test scheme for SOC. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (ASP-DAC, 2005)

Finite State Machine Synthesis for At-Speed Oscillation Testability. - Katherine Shu-Min Li; Chung-Len Lee 001; Tagin Jiang; Chauchin Su; Jwu E. Chen (Asian Test Symposium, 2005)

A Scan Matrix Design for Low Power Scan-Based Test. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen (Asian Test Symposium, 2005)

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. - Shih Ping Lin 001; Chung-Len Lee 001; Jwu E. Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (ITC, 2006)

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. - Katherine Shu-Min Li; Chauchin Su; Yao-Wen Chang; Chung-Len Lee 001; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (J. Electron. Test., 2007)

Multilevel Full-Chip Routing With Testability and Yield Enhancement. - Katherine Shu-Min Li; Yao-Wen Chang; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. - Shih-Ping Lin 001; Chung-Len Lee 001; Jwu-E Chen; Ji-Jan Chen; Kun-Lun Luo; Wen Ching Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. - Weibo Hu; Chung Len Lee 001; Xin'an Wang (DELTA, 2008)

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. - Katherine Shu-Min Li; Chung-Len Lee 001; Chauchin Su; Jwu E. Chen (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Modeling and testing of interference faults in the nano NAND Flash memory. - Jin Zha; Xiaole Cui; Chung Len Lee 001 (DATE, 2012)

A novel test scheme for NAND flash memory based on built-in oscillator ring. - Si Chen; Xiaole Cui; Chung Len Lee 001 (ASICON, 2013)

New DfT architectures for 3D-SICs with a wireless test port. - Yibo He; Xiaole Cui; Chung Len Lee 001; Xiaoxin Cui; Yufeng Jin (ASICON, 2013)

Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. - Weijia Ma; Xiaole Cui; Chung Len Lee 001 (ASICON, 2013)

A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. - Zhengyu Qian; Xiaole Cui; Bo Wang 016; Xiangrong Zhang; Chung Len Lee 001 (ASICON, 2013)

A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. - Xuan Yang; Xiaole Cui; Chao Wang; Chung Len Lee 001 (ASICON, 2013)

A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. - Xiangrong Zhang; Xiaole Cui; Bo Wang 016; Chung Len Lee 001 (ISCAS, 2013)

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. - Zuolin Cheng; Xiaole Cui; Xiaoxin Cui; Chung Len Lee 001 (IET Comput. Digit. Tech., 2015)

A snake addressing scheme for phase change memory testing. - Xiaole Cui; Zuolin Cheng; Chung-Len Lee 001; Xinnan Lin; Yiqun Wei; Xiaogang Chen; Zhitang Song (Sci. China Inf. Sci., 2016)