A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. - Chien-Yu Lu; Ching-Te Chuang; Shyh-Jye Jou; Ming-Hsien Tu; Ya-Ping Wu; Chung-Ping Huang; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (IEEE Trans. Very Large Scale Integr. Syst., 2015)