PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. - Pei-Chen Wu; Yi-Ping Kuo; Chung-Shiang Wu; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (SoCC, 2014)

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. - Chung-Shiang Wu; Kai-Chun Lin; Yi-Ping Kuo; Po-Hung Chen; Yuan-Hua Chu; Wei Hwang (ISCAS, 2015)

20.10 A 50nW-to-10mW output power tri-mode digital buck converter with self-tracking zero current detection for photovoltaic energy harvesting. - Po-Hung Chen; Chung-Shiang Wu; Kai-Chun Lin (ISSCC, 2015)

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. - Yi-Ping Kuo; Po-Tsang Huang; Chung-Shiang Wu; Yu-Jie Liang; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (VLSI-DAT, 2015)

A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting. - Po-Hung Chen; Chung-Shiang Wu; Kai-Chun Lin (IEEE J. Solid State Circuits, 2016)

Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. - Chung-Shiang Wu; Makoto Takamiya; Takayasu Sakurai (CICC, 2017)

Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. - Chung-Shiang Wu; Hui-Hsuan Lee; Po-Hung Chen; Wei Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. - Chung-Shiang Wu; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper). - Todd Takken; Andrew Ferencz; Chung-Shiang Wu; Liam McAuliffe; Tianyu Jia; Xin Zhang (VLSI Circuits, 2019)