Crossbar array of selector-less TaOx/TiO2 bilayer RRAM. - Chun-Tse Chou; Boris Hudec; Chung-Wei Hsu; Wei-Li Lai; Chih-Cheng Chang; Tuo-Hung Hou (Microelectron. Reliab., 2015)

3D resistive RAM cell design for high-density storage class memory - a review. - Boris Hudec; Chung-Wei Hsu; I-Ting Wang; Wei-Li Lai; Che-Chia Chang; Taifang Wang; Karol Fröhlich; Chia-Hua Ho; Chen-Hsi Lin; Tuo-Hung Hou (Sci. China Inf. Sci., 2016)

A 12-bit 40-MS/s calibration-free SAR ADC. - Chung-Wei Hsu; Li-Jen Chang; Chun-Po Huang; Soon-Jyh Chang (ISCAS, 2017)

A 12-b 40-MS/s Calibration-Free SAR ADC. - Chung-Wei Hsu; Soon-Jyh Chang; Chun-Po Huang; Li-Jen Chang; Ya-Ting Shyu; Chih-Huei Hou; Hwa-An Tseng; Chih-Yuan Kung; Huan-Jui Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. - Hong-Han Lien; Chung-Wei Hsu; Tian-Sheuan Chang (ISCAS, 2021)

A Novel Reversible Data Hiding Method with Contrast Enhancement for Color Medical Images. - Chin-Feng Lee; Chung-Wei Hsu; Iuon-Chang Lin (ICMHI, 2023)

A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm. - Wei-Hsin Tseng; Willy Lin; Chung-Wei Hsu; Chang-Yang Huang; Yu-Sian Lin; Hung-Yi Huang; HsinWei Chen; Sheng-Hui Liao; Kuan-Dar Chen; Jon Strange; Gabriele Manganaro (ISSCC, 2023)