Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD. - Kenneth D. Boese; Andrew B. Kahng; Chung-Wen Albert Tsao (EURO-DAC, 1993)

Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. - Chung-Wen Albert Tsao; Andrew B. Kahng (EURO-DAC, 1994)

Low-cost single-layer clock trees with exact zero Elmore delay skew. - Andrew B. Kahng; Chung-Wen Albert Tsao (ICCAD, 1994)

On the Bounded-Skew Clock and Steiner Routing Problems. - Dennis J.-H. Huang; Andrew B. Kahng; Chung-Wen Albert Tsao (DAC, 1995)

Bounded-skew clock and Steiner routing under Elmore delay. - Jason Cong; Andrew B. Kahng; Cheng-Kok Koh; Chung-Wen Albert Tsao (ICCAD, 1995)

Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods. - T. C. Hu; Andrew B. Kahng; Chung-Wen Albert Tsao (INFORMS J. Comput., 1995)

Planar-DME: a single-layer zero-skew clock tree router. - Andrew B. Kahng; Chung-Wen Albert Tsao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

More Practical Bounded-Skew Clock Routing. - Andrew B. Kahng; Chung-Wen Albert Tsao (DAC, 1997)

Practical Bounded-Skew Clock Routing. - Andrew B. Kahng; Chung-Wen Albert Tsao (J. VLSI Signal Process., 1997)

Bounded-skew clock and Steiner routing. - Jason Cong; Andrew B. Kahng; Cheng-Kok Koh; Chung-Wen Albert Tsao (ACM Trans. Design Autom. Electr. Syst., 1998)

Power Supply Noise Suppression via Clock Skew Scheduling. - Wai-Ching Douglas Lam; Cheng-Kok Koh; Chung-Wen Albert Tsao (ISQED, 2002)

UST/DME: a clock tree router for general skew constraints. - Chung-Wen Albert Tsao; Cheng-Kok Koh (ACM Trans. Design Autom. Electr. Syst., 2002)

Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. - Wai-Ching Douglas Lam; Cheng-Kok Koh; Chung-Wen Albert Tsao (ISQED, 2003)