LIBRA - a library-independent framework for post-layout performance optimization. - Chung-Yang Huang; Yucheng Wang; Kwang-Ting Cheng (ISPD, 1998)

Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. - Chung-Yang Huang; Kwang-Ting Cheng (DAC, 2000)

Static property checking using ATPG vs. BDD techniques. - Chung-Yang Huang; Bwolen Yang; Huan-Chih Tsai; Kwang-Ting Cheng (ITC, 2000)

AQUILA: An Equivalence Checking System for Large Sequential Designs. - Shi-Yu Huang; Kwang-Ting Cheng; Kuang-Chien Chen; Chung-Yang Huang; Forrest Brewer (IEEE Trans. Computers, 2000)

An analysis of ATPG and SAT algorithms for formal verification. - Ganapathy Parthasarathy; Chung-Yang Huang; Kwang-Ting Cheng (HLDVT, 2001)

Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. - Chung-Yang Huang; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

QuteSAT: a robust circuit-based SAT solver for complex circuit structure. - Chi-An Wu; Ting-Hao Lin; Chih-Chun Lee; Chung-Yang Huang (DATE, 2007)

Scalable exploration of functional dependency by interpolation and incremental SAT solving. - Chih-Chun Lee; Jie-Hong Roland Jiang; Chung-Yang Huang; Alan Mishchenko (ICCAD, 2007)

QuteIP: An IP qualification framework for System on Chip. - Hsing-Chih Hung; Ting-Hao Lin; Chung-Yang Huang (SoCC, 2007)

Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. - Chao-Yue Lai; Chung-Yang Huang; Kei-Yong Khoo (DATE, 2008)

SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. - Chi-An Wu; Ting-Hao Lin; Shao-Lun Huang; Chung-Yang Huang (ASP-DAC, 2009)

A false-path aware formal static timing analyzer considering simultaneous input transitions. - Shihheng Tsai; Chung-Yang Huang (DAC, 2009)

Interpolant generation without constructing resolution graph. - Chih-Jen Hsu; Shao-Lun Huang; Chi-An Wu; Chung-Yang Huang (ICCAD, 2009)

Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. - Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang (ASP-DAC, 2010)

A unified multi-corner multi-mode static timing analysis engine. - Jing-Jia Nian; Shihgeng Tsai; Chung-Yang (Ric) Huang (ASP-DAC, 2010)

Automatic constraint generation for guided random simulation. - Hu-Hsi Yeh; Chung-Yang Huang (ASP-DAC, 2010)

Formal deadlock checking on high-level SystemC designs. - Chun-Nan Chou; Chang-Hong Hsu; Yueh-Tung Chao; Chung-Yang Huang (ICCAD, 2010)

A robust functional ECO engine by SAT proof minimization and interpolation techniques. - Bo-Han Wu; Chun-Ju Yang; Chung-Yang Huang; Jie-Hong Roland Jiang (ICCAD, 2010)

To SAT or Not to SAT: Scalable Exploration of Functional Dependency. - Jie-Hong Roland Jiang; Chih-Chun Lee; Alan Mishchenko; Chung-Yang Huang (IEEE Trans. Computers, 2010)

A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. - Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; Chung-Yang Huang (ASP-DAC, 2011)

SoC HW/SW verification and validation. - Chung-Yang Huang; Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang (ASP-DAC, 2011)

Using SAT-based Craig interpolation to enlarge clock gating functions. - Ting-Hao Lin; Chung-Yang (Ric) Huang (DAC, 2011)

Interpolation-based incremental ECO synthesis for multi-error logic rectification. - Kai-Fu Tang; Chi-An Wu; Po-Kai Huang; Chung-Yang (Ric) Huang (DAC, 2011)

Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. - Yu-Fu Yeh; Chung-Yang Huang; Chi-An Wu; Hsin-Cheng Lin (DATE, 2011)

Match and replace - A functional ECO engine for multi-error circuit rectification. - Shao-Lun Huang; Wei-Hsun Lin; Chung-Yang (Ric) Huang (ICCAD, 2011)

Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. - Bo-Han Wu; Chun-Ju Yang; Chia-Cheng Tso; Chung-Yang (Ric) Huang (ICCAD, 2011)

Property-specific sequential invariant extraction for SAT-based unbounded model checking. - Hu-Hsi Yeh; Cheng-Yin Wu; Chung-Yang (Ric) Huang (ICCAD, 2011)

A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. - Shihheng Tsai; Man-Yu Li; Chung-Yang Huang (ASP-DAC, 2012)

Symbolic model checking on SystemC designs. - Chun-Nan Chou; Yen-Sheng Ho; Chiao Hsieh; Chung-Yang (Ric) Huang (DAC, 2012)

Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. - Kai-Fu Tang; Po-Kai Huang; Chun-Nan Chou; Chung-Yang Huang (DATE, 2012)

A robust general constrained random pattern generator for constraints with variable ordering. - Bo-Han Wu; Chung-Yang (Ric) Huang (ICCAD, 2012)

QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification. - Hu-Hsi Yeh; Cheng-Yin Wu; Chung-Yang (Ric) Huang (TACAS, 2012)

A robust constraint solving framework for multiple constraint sets in constrained random verification. - Bo-Han Wu; Chung-Yang (Ric) Huang (DAC, 2013)

Conquering the scheduling alternative explosion problem of SystemC symbolic simulation. - Chun-Nan Chou; Chen-Kai Chu; Chung-Yang (Ric) Huang (ICCAD, 2013)

Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. - Shao-Lun Huang; Wei-Hsun Lin; Po-Kai Huang; Chung-Yang Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. - Yu-Fu Yeh; Hsin-Cheng Lin; Chung-Yang Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Adaptive interpolation-based model checking. - Chien-Yu Lai; Cheng-Yin Wu; Chung-Yang (Ric) Huang (ASP-DAC, 2014)

A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking. - Cheng-Yin Wu; Chi-An Wu; Chien-Yu Lai; Chung-Yang (Ric) Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification. - Bo-Han Wu; Chun-Ju Yang; Chung-Yang Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Automatic abstraction refinement of TR for PDR. - Kuan Fan; Ming-Jen Yang; Chung-Yang Huang (ASP-DAC, 2016)

Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. - Kuan-Lun Tseng; Yen-Liang Lin; Winston H. Hsu; Chung-Yang Huang (CVPR, 2017)

Compatible Equivalence Checking of X-Valued Circuits. - Yu-Neng Wang; Yun-Rong Luo; Po-Chun Chien; Ping-Lun Wang; Hao-Ren Wang; Wan-Hsuan Lin; Jie-Hong Roland Jiang; Chung-Yang (Ric) Huang (ICCAD, 2021)

Qubit Mapping Toward Quantum Advantage. - Chin-Yi Cheng; Chien-Yi Yang; Ren-Chu Wang; Yi-Hsiang Kuo; Hao-Chung Cheng; Chung-Yang Huang (CoRR, 2022)