Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer. - Chunmeng Dou; Kuniyuki Kakushima; Parhat Ahmet; Kazuo Tsutsui; Akira Nishiyama; Nobuyuki Sugii; Kenji Natori; Takeo Hattori; Hiroshi Iwai (Microelectron. Reliab., 2012)

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. - Chunmeng Dou; Dennis Lin; Abhitosh Vais; Tsvetan Ivanov; Han-Ping Chen; Koen Martens; Kuniyuki Kakushima; Hiroshi Iwai; Yuan Taur; Aaron Thean; Guido Groeseneken (Microelectron. Reliab., 2014)

Characterization of interface state density of three-dimensional Si nanostructure by charge pumping measurement. - Chunmeng Dou; Tomoya Shoji; Kazuhiro Nakajima; Kuniyuki Kakushima; Parhat Ahmet; Yoshinori Kataoka; Akira Nishiyama; Nobuyuki Sugii; Hitoshi Wakabayashi; Kazuo Tsutsui; Kenji Natori; Hiroshi Iwai (Microelectron. Reliab., 2014)

Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing. - Chunmeng Dou; Wei-Hao Chen; Yi-Ju Chen; Huan-Ting Lin; Wei-Yu Lin; Mon-Shu Ho; Meng-Fan Chang (ASICON, 2017)

An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron. - Jinsong Wei; Jilin Zhang; Xumeng Zhang; Zuheng Wu; Chunmeng Dou; Tuo Shi; Hong Chen 002; Qi Liu 010 (ASICON, 2019)

A 0.75 V reference clamping sense amplifier for low-power high-density ReRAM with dynamic pre-charge technique. - Jiahao Yin; Chunmeng Dou; Danian Dong; Jie Yu 027; Xiaoxin Xu; Qing Luo; Tiancheng Gong; Lu Tai; Peng Yuan; Xiaoyong Xue; Ming Liu 022; Hangbing Lv (IEICE Electron. Express, 2019)

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices. - Sitao Zeng; Yuxin Zhang; Zhiguo Zhu; Zhaolong Qin; Chunmeng Dou; Xin Si; Qiang Li 001 (AICAS, 2021)

Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory. - Linfang Wang; Wang Ye; Junjie An; Chunmeng Dou; Qi Liu 010; Meng-Fan Chang; Ming Liu 022 (ISCAS, 2021)

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. - Yuxin Zhang; Sitao Zeng; Zhiguo Zhu; Zhaolong Qin; Chen Wang 130; Jingjing Li 001; Sanfeng Zhang; Yajuan He; Chunmeng Dou; Xin Si; Meng-Fan Chang; Qiang Li 021 (ISCAS, 2021)

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. - Linfang Wang; Wang Ye; Chunmeng Dou; Xin Si; Xiaoxin Xu; Jing Liu 035; Dashan Shang; Jianfeng Gao 005; Feng Zhang 014; Yongpan Liu; Meng-Fan Chang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 55nm 32Mb Digital Flash CIM Using Compressed LUT Multiplier and Low Power WL Voltage Trimming Scheme for AI Edge Inference. - Hongyang Hu; Zi Wang; Xiaoxin Xu; Kai Xi; Kun Zhang; Junyu Zhang; Chunmeng Dou (APCCAS, 2022)

RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference. - Linfang Wang; Junjie An; Wang Ye; Weizeng Li; Hanghang Gao; Yangu He; Jianfeng Gao 005; Jinshan Yue; Lingyan Fan; Chunmeng Dou (APCCAS, 2022)

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory. - Woyu Zhang; Shaocong Wang; Yi Li 049; Xiaoxin Xu; Danian Dong; Nanjia Jiang; Fei Wang; Zeyu Guo 002; Renrui Fang; Chunmeng Dou; Kai Ni; Zhongrui Wang; et al. (VLSI Technology and Circuits, 2022)

Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory. - Yi Li 049; Woyu Zhang; Xiaoxin Xu; Yifan He 003; Danian Dong; Nanjia Jiang; Fei Wang; Zeyu Guo 002; Shaocong Wang; Chunmeng Dou; Yongpan Liu; Zhongrui Wang; et al. (Adv. Intell. Syst., 2022)

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Xiaoyu Feng; Yifan He 002; Wenyu Sun; Zhixiao Zhang; Xin Si; Ruhui Liu; Zi Wang; Meng-Fan Chang; Chunmeng Dou; et al. (IEEE J. Solid State Circuits, 2022)

A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. - Jianguo Yang; Qing Luo; Xiaoyong Xue; Haijun Jiang; Qiqiao Wu; Zhongze Han; Yue Cao; Yongkang Han; Chunmeng Dou; Hangbing Lv; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI. - Yi Li 049; Jia Chen; Linfang Wang; Woyu Zhang; Zeyu Guo 002; Jun Wang; Yongkang Han; Zhi Li 070; Fei Wang; Chunmeng Dou; Xiaoxin Xu; Jianguo Yang; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. - Hongyang Hu; Xiwei Wang; Zi Wang; Haiyang Zhou; Danian Dong; Jinshan Yue; Wan Pang; Xiaoxin Xu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. - Weizeng Li; Linfang Wang; Zhi Li 062; Wang Ye; Zhidao Zhou; Haiyang Zhou; Hanghang Gao; Jinshan Yue; Hongyang Hu; Fengman Liu; Qing Luo; Chunmeng Dou (ISCAS, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. - Zhuoyu Dai; Shengzhe Yan; Zhaori Cong; Zeyu Guo 002; Yifan He 002; Wenyu Sun; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu; Ming Liu 022 (VLSI Technology and Circuits, 2024)

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s). - Menggan Liu; Zhi Li 062; Wendong Lu; Kaifei Chen; Jiebin Niu; Fuxi Liao; Zijing Wu; Congyan Lu; Weizeng Li; Di Geng; Nianduan Lu; Chunmeng Dou; et al. (VLSI Technology and Circuits, 2024)

Binary-Stochasticity-Enabled Highly Efficient Neuromorphic Deep Learning Achieves Better-than-Software Accuracy. - Yang Li 203; Wei Wang 209; Ming Wang; Chunmeng Dou; Zhengyu Ma; Huihui Zhou; Peng Zhang 077; Nicola Lepri; Xumeng Zhang; Qing Luo; Xiaoxin Xu; Guanhua Yang; et al. (Adv. Intell. Syst., 2024)

A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. - Qiqiao Wu; Yue Cao; Qing Luo; Haijun Jiang; Zhongze Han; Yongkang Han; Chunmeng Dou; Hangbing Lv; Qi Liu 010; Jianguo Yang; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

2T2R RRAM-Based In-Memory Hyperdimensional Computing Encoder for Spatio-Temporal Signal Processing. - Zhi Li 070; Rui Bao; Woyu Zhang; Fei Wang; Jun Wang; Renrui Fang; Haoxiong Ren; Ning Lin; Jinshan Yue; Chunmeng Dou; Zhongrui Wang; Dashan Shang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Fully Binarized Graph Convolutional Network Accelerator Based on In-Memory Computing with Resistive Random-Access Memory. - Woyu Zhang; Zhi Li 070; Xinyuan Zhang; Fei Wang; Shaocong Wang; Ning Lin; Yi Li 049; Jun Wang; Jinshan Yue; Chunmeng Dou; Xiaoxin Xu; Zhongrui Wang; et al. (Adv. Intell. Syst., 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)

A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics. - Shengzhe Yan; Zhaori Cong; Zi Wang; Zhuoyu Dai; Zeyu Guo 002; Zhihang Qian; Xufan Li; Xu Zheng; Chuanke Chen; Nianduan Lu; Chunmeng Dou; Guanhua Yang; et al. (Sci. China Inf. Sci., 2025)

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. - Wang Ye; Hanghang Gao; Zhidao Zhou; Linfang Wang; Weizeng Li; Zhi Li 062; Jinshan Yue; Xiaoxin Xu; Jianguo Yang; Hongyang Hu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. - Zhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo 002; Zhaori Cong; Yifan He 002; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)