High bandwidth memory(HBM) with TSV technique. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Sangmuk Oh; Hyun Sung Lee; Ki Hun Kwon; et al. (ISOCC, 2016)

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Yeon Ok Kim; Jae-Hwan Kim; Jin Ho Kim; et al. (ISSCC, 2016)

A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. - Jin-Hee Cho; Jihwan Kim; Wooyoung Lee; Dong-Uk Lee; Tae-Kyun Kim 002; Heat Bit Park; Chunseok Jeong; Myeong-Jae Park; Seung Geun Baek; Seokwoo Choi; Byung Kuk Yoon; Young Jae Choi; et al. (ISSCC, 2018)

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller. - Seong Ju Lee; Byung Deuk Jeon; Kyeong Pil Kang; Dong Yoon Ka; Na Yeon Kim; Yongseop Kim; Yunseok Hong; Mankeun Kang; Jinyong Min; Mingyu Lee; Chunseok Jeong; Kwandong Kim; et al. (ISSCC, 2019)

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. - Dong-Uk Lee; Ho Sung Cho; Jihwan Kim; Young Jun Ku; Sangmuk Oh; Chul Dae Kim; Hyun Woo Kim; Wooyoung Lee; Tae-Kyun Kim 001; Tae Sik Yun; Min Jeong Kim; SeungGyeon Lim; et al. (ISSCC, 2020)

Newton: A DRAM-maker's Accelerator-in-Memory (AiM) Architecture for Machine Learning. - Mingxuan He; Choungki Song; Ilkon Kim; Chunseok Jeong; Seho Kim; Il Park 001; Mithuna Thottethodi; T. N. Vijaykumar (MICRO, 2020)

System Architecture and Software Stack for GDDR6-AiM. - Yongkee Kwon; Kornijcuk Vladimir; Nahsung Kim; Woojae Shin; Jongsoon Won; Minkyu Lee; Hyunha Joo; Haerang Choi; Guhyun Kim; Byeongju An; Jeongbin Kim 001; Jaewook Lee; et al. (HCS, 2022)

Holistic approaches to memory solutions for the Autonomous Driving Era. - Daeyong Shim; Chunseok Jeong; Euncheol Lee; Junmo Kang; Seokcheol Yoon; Yongkee Kwon; Il Park 001; Hyun Ahn; Seonyong Cha; Jinkook Kim (ISCAS, 2022)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)

Memory-Centric Computing with SK Hynix's Domain-Specific Memory. - Yongkee Kwon; Guhyun Kim; Nahsung Kim; Woojae Shin; Jongsoon Won; Hyunha Joo; Haerang Choi; Byeongju An; Gyeongcheol Shin; Dayeon Yun; Jeongbin Kim 001; Changhyun Kim; et al. (HCS, 2023)

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. - Dae-Han Kwon; Seongju Lee; Kyuyoung Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dongyoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; et al. (IEEE J. Solid State Circuits, 2023)

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System. - Minseok Seo; Xuan Truong Nguyen; Seok Joong Hwang; Yongkee Kwon; Guhyun Kim; Chanwook Park; Ilkon Kim; Jaehan Park; Jeongbin Kim 001; Woojae Shin; Jongsoon Won; Haerang Choi; et al. (ASPLOS (3), 2024)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)

Analog Circuit Design Automation via Sequential RL Agents and Gm/ID Methodology. - Sungweon Hong; Yunseob Tae; Dongjun Lee; Gijin Park; Jaemyung Lim; Kyungjun Cho; Chunseok Jeong; Myeong-Jae Park; Songnam Hong 001; Jaeduk Han (IEEE Access, 2024)