The study of parallel simulation processing based on MPP technology. - Yang Shi; Chenxi Zhang; Chunyuan Zhang (APDC, 1997)

Multiple-Dimension Scalable Adaptive Stream Architecture. - Mei Wen; Nan Wu 003; Haiyan Li; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2004)

A Case of SCMP with TLS. - Jianzhuang Lu; Chunyuan Zhang; Zhiying Wang; Yun Cheng; Dan Wu (ISPA, 2004)

A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. - Mei Wen; Chunyuan Zhang; Nan Wu 003; Haiyan Li; Li Li 005 (ISPA, 2004)

A Stream Architecture Supporting Multiple Stream Execution Models. - Nan Wu 003; Mei Wen; Haiyan Li; Li Li 005; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2005)

Accelerated Motion Estimation of H.264 on Imagine Stream Processor. - Haiyan Li; Mei Wen; Chunyuan Zhang; Nan Wu 003; Li Li 005; Changqing Xun (ICIAR, 2005)

Multiple-Morphs Adaptive Stream Architecture. - Mei Wen; Nan Wu 003; Haiyan Li; Chunyuan Zhang (J. Comput. Sci. Technol., 2005)

Analysis and Performance Results of a fluid dynamics Application on MASA Stream Processor. - Mei Wen; Nan Wu 003; Changqing Xun; Wei Wu; Chunyuan Zhang (ACIS-ICIS, 2006)

Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. - Mei Wen; Nan Wu 003; Changqing Xun; Wei Wu; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2006)

Register Allocation on Stream Processor with Local Register File. - Nan Wu 003; Mei Wen; Ju Ren 002; Yi He 008; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2006)

A Streaming Implementation of Transform and Quantization in H.264. - Haiyan Li; Chunyuan Zhang; Li Li 005; Ming Pang (HPCC, 2006)

The Process of Synchronization in Dual Redundant Fault-Tolerant System. - Dong Liu 022; Chunyuan Zhang; Rui Li 051 (IIP, 2006)

Prediction-Table Based Fault-Tolerant Real-Time Scheduling Algorithm. - Dong Liu 022; Chunyuan Zhang; Rui Li 051 (PDCAT, 2006)

A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. - Nan Wu 003; Qianming Yang; Mei Wen; Yi He 008; Changqing Xun; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2007)

The Design on SEU-Tolerant Information Processing System of the On-Board-Computer. - Ying Huang; Chunyuan Zhang; Dong Liu 022; Yi Li; Sheng-xin Weng (APPT, 2007)

FT64: Scientific Computing with Streams. - Mei Wen; Nan Wu 003; Chunyuan Zhang; Wei Wu; Qianming Yang; Changqing Xun (HiPC, 2007)

Efficient Broadcasting in Multi-radio Multi-channel and Multi-hop Wireless Networks Based on Self-pruning. - Li Li 005; Bin Qin; Chunyuan Zhang; Haiyan Li (HPCC, 2007)

Quantification of Cut Sequence Set for Fault Tree Analysis. - Dong Liu 022; Chunyuan Zhang; Weiyan Xing; Rui Li 051; Haiyan Li (HPCC, 2007)

A Fault-Tolerant Real-Time Scheduling Algorithm in Software Fault-Tolerant Module. - Dong Liu 022; Weiyan Xing; Rui Li 051; Chunyuan Zhang; Haiyan Li (International Conference on Computational Science (4), 2007)

Cut Sequence Set Generation for Fault Tree Analysis. - Dong Liu 022; Weiyan Xing; Chunyuan Zhang; Rui Li 051; Haiyan Li (ICESS, 2007)

Broadcasting in Multi-Radio Multi-Channel and Multi-Hop Wireless Networks. - Li Li 005; Bin Qin; Chunyuan Zhang (MMNS, 2007)

Stream Algorithm for 4*4 Integer Transform in H.264. - Haiyan Li; Chunyuan Zhang; Ju Ren 002; Li Li 005; Dong Liu 022 (MUE, 2007)

FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. - Yi He 008; Ju Ren 002; Qianming Yang; Mei Wen; Nan Wu 003; Chunyuan Zhang (ACSAC, 2008)

Load scheduling: Reducing pressure on distributed register files for free. - Mei Wen; Nan Wu 003; Maolin Guan; Chunyuan Zhang (ASP-DAC, 2008)

Improving the Quality of Graduate Education by Association Rules Analysis. - Yi Fang; Chunyuan Zhang (FSKD (4), 2008)

On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. - Mei Wen; Nan Wu 003; Chunyuan Zhang; Qianming Yang; Ju Ren 002; Yi He 008; Wei Wu; Jun Chai; Maolin Guan; Changqing Xun (IEEE Micro, 2008)

Transform coding on programmable stream processors. - Haiyan Li; Chunyuan Zhang; Li Li 005; Ju Ren 002 (J. Supercomput., 2008)

Joint Channel Width Adaptation, Topology Control, and Routing for Multi-Radio Multi-Channel Wireless Mesh Networks. - Li Li; Chunyuan Zhang (CCNC, 2009)

Software parallel CAVLC encoder based on stream processing. - Ju Ren 002; Yi He 008; Wei Wu; Mei Wen; Nan Wu 003; Chunyuan Zhang (ESTIMedia, 2009)

Cache streamization for high performance stream processor. - Nan Wu 003; Mei Wen; Ju Ren 002; Yi He 008; Changqing Xun; Wei Wu; Chunyuan Zhang (HiPC, 2009)

Streaming HD H.264 encoder on programmable processors. - Nan Wu 003; Mei Wen; Wei Wu; Ju Ren 002; Huayou Su; Changqing Xun; Chunyuan Zhang (ACM Multimedia, 2009)

Interference-aware Broadcast Routing and Channel Assignment for Multi-Radio Wireless Mesh Networks. - Li Li 005; Bin Qin; Chunyuan Zhang (VTC Fall, 2009)

QoS-aware on-demand channel width adaptation protocols for multi-radio ad-hoc networks. - Li Li 005; Chunyuan Zhang; Yanhua Li (WCNC, 2009)

Optimal Channel Width Adaptation, Logical Topology Design, and Routing in Wireless Mesh Networks. - Li Li 005; Chunyuan Zhang (EURASIP J. Wirel. Commun. Netw., 2009)

SAT: A Stream Architecture Template for Embedded Applications. - Qianming Yang; Nan Wu 003; Mei Wen; Yi He 008; Huayou Su; Chunyuan Zhang (CIT, 2010)

Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. - Yi He 008; Ju Ren 002; Mei Wen; Qianming Yang; Nan Wu 003; Chunyuan Zhang (DSD, 2010)

A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors. - Ju Ren 002; Mei Wen; Chunyuan Zhang; Huayou Su; Yi He 008; Nan Wu 003 (FCST, 2010)

Importance Measure Method for Dynamic Fault Tree Based on Isomorphic Node. - Hong-Lin Zhang; Chunyuan Zhang; Dong Liu 022; Gui-Wu Xie (ICICA (LNCS), 2010)

A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. - Huayou Su; Nan Wu 003; Chunyuan Zhang; Mei Wen; Ju Ren 002 (ICIG, 2011)

High-efficient software parallel CAVLC encoder based on programmable stream processor. - Huayou Su; Chunyuan Zhang; Jun Chai; Mei Wen; Nan Wu 003; Ju Ren 002 (ACM Multimedia, 2011)

A high-efficient software parallel CAVCL encoder based on GPU. - Huayou Su; Chunyuan Zhang; Jun Chai; Mei Wen; Nan Wu 003; Ju Ren 002 (TSP, 2011)

Tiled Multi-Core Stream Architecture. - Nan Wu 003; Qianming Yang; Mei Wen; Yi He 008; Ju Ren 002; Maolin Guan; Chunyuan Zhang (Trans. High Perform. Embed. Archit. Compil., 2011)

Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. - Mei Wen; Huayou Su; Wenjie Wei; Nan Wu 003; Xing Cai; Chunyuan Zhang (CLUSTER, 2012)

The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). - Mei Wen; Nan Wu 003; Qianming Yang; Chunyuan Zhang; Liang Zhao (FPGA, 2012)

Extending BORPH for shared memory reconfigurable computers. - Changqing Xun; Mei Wen; Nan Wu 003; Chunyuan Zhang; Hayden Kwok-Hay So (FPL, 2012)

Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. - Yi He 008; Maolin Guan; Chunyuan Zhang; Tian Tian; Qianming Yang (HPCC-ICESS, 2012)

Parallelization Design of Irregular Algorithms of Video Processing on GPUs. - Huayou Su; Jun Chai; Mei Wen; Ju Ren 002; Chunyuan Zhang (ICME, 2012)

A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. - Nan Wu 003; Mei Wen; Huayou Su; Ju Ren 002; Chunyuan Zhang (ICPADS, 2012)

Architecting Dependable Many-Core Processors Using Core-Level Dynamic Redundancy. - Wentao Jia; Chunyuan Zhang; Jian Fu; Rui Li 051 (ISCTCS, 2012)

Improving Performance of GPU Specific OpenCL Program on CPUs. - Qiang Lan; Changqing Xun; Mei Wen; Huayou Su; Lifang Liu; Chunyuan Zhang (PDCAT, 2012)

Identification method of independent module for dynamic fault tree with interdependent basic events and repeated events. - Hong-Lin Zhang; Chunyuan Zhang; Dong Liu 022 (Int. J. Comput. Appl. Technol., 2012)

ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. - Nan Wu 003; Yuran Qiao; Mei Wen; Chunyuan Zhang (APPT, 2013)

Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform. - Dong Chen 015; Changqing Xun; Dafei Huang; Mei Wen; Chunyuan Zhang (HPCC/EUC, 2013)

Device View Redundancy: An Adaptive Low-Overhead Fault Tolerance Mechanism for Many-Core System. - Wentao Jia; Chunyuan Zhang; Jian Fu (HPCC/EUC, 2013)

Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). - Jing Yang; Jun Chai; Mei Wen; Nan Wu 003; Chunyuan Zhang (HPCC/EUC, 2013)

Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. - Huayou Su; Nan Wu 003; Mei Wen; Chunyuan Zhang; Xing Cai (ICCS, 2013)

On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. - Huayou Su; Nan Wu 003; Mei Wen; Chunyuan Zhang; Xing Cai (ICPADS, 2013)

An Adaptive Low-Overhead Mechanism for Dependable General-Purpose Many-Core Processors. - Wentao Jia; Rui Li 051; Chunyuan Zhang (ICT-EurAsia, 2013)

On-demand thread-level fault detection in a concurrent programming environment. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ICSAMOS, 2013)

On the GPU Performance of 3D Stencil Computations Implemented in OpenCL. - Huayou Su; Nan Wu 003; Mei Wen; Chunyuan Zhang; Xing Cai (ISC, 2013)

Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. - Jun Chai; Mei Wen; Nan Wu 003; Dafei Huang; Jing Yang; Xing Cai; Chunyuan Zhang; Qianming Yang (IEICE Trans. Inf. Syst., 2013)

Efficient fine-grained shared buffer management for multiple OpenCL devices. - Changqing Xun; Dong Chen 015; Qiang Lan; Chunyuan Zhang (J. Zhejiang Univ. Sci. C, 2013)

Resource-efficient utilization of CPU/GPU-based heterogeneous supercomputers for Bayesian phylogenetic inference. - Jun Chai; Huayou Su; Mei Wen; Xing Cai; Nan Wu 003; Chunyuan Zhang (J. Supercomput., 2013)

Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. - Qianming Yang; Mei Wen; Nan Wu 003; Chunyuan Zhang (J. Supercomput., 2013)

Shape Similarity Analysis by Self-Tuning Locally Constrained Mixed-Diffusion. - Lei Luo 002; Chunhua Shen; Chunyuan Zhang; Anton van den Hengel (IEEE Trans. Multim., 2013)

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ARES, 2014)

A fault detection mechanism in a Data-flow scheduled Multithreaded processor. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (DATE, 2014)

Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. - Dafei Huang; Mei Wen; Changqing Xun; Dong Chen 015; Xing Cai; Yuran Qiao; Nan Wu 003; Chunyuan Zhang (Euro-Par, 2014)

Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. - Xinnan Dong; Jun Chai; Jing Yang; Mei Wen; Nan Wu 003; Xing Cai; Chunyuan Zhang; Zhaoyun Chen (ICA3PP (2), 2014)

High efficient sedimentary basin simulations on hybrid CPU-GPU clusters. - Mei Wen; Huayou Su; Wenjie Wei; Nan Wu 003; Xing Cai; Chunyuan Zhang (Clust. Comput., 2014)

Enable Scale and Aspect Ratio Adaptability in Visual Tracking with Detection Proposals. - Dafei Huang; Lei Luo 002; Mei Wen; Zhaoyun Chen; Chunyuan Zhang (BMVC, 2015)

Fast tracking via context depth model learning. - Zhaoyun Chen; Lei Luo 002; Mei Wen; Chunyuan Zhang (ICIP, 2015)

Communication-hiding programming for clusters with multi-coprocessor nodes. - Xinnan Dong; Mei Wen; Jun Chai; Xing Cai; Mandan Zhao; Chunyuan Zhang (Concurr. Comput. Pract. Exp., 2015)

Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. - Dafei Huang; Changqing Xun; Nan Wu 003; Mei Wen; Chunyuan Zhang; Xing Cai; Qianming Yang (IEICE Trans. Inf. Syst., 2015)

Towards simulation of subcellular calcium dynamics at nanometre resolution. - Jun Chai; Johan Hake; Nan Wu 003; Mei Wen; Xing Cai; Glenn Terje Lines; Jing Yang; Huayou Su; Chunyuan Zhang; Xiangke Liao (Int. J. High Perform. Comput. Appl., 2015)

A Computational Model of the Short-Cut Rule for 2D Shape Decomposition. - Lei Luo 002; Chunhua Shen; Xinwang Liu 002; Chunyuan Zhang (IEEE Trans. Image Process., 2015)

An analytical GPU performance model for 3D stencil computations from the angle of data traffic. - Huayou Su; Xing Cai; Mei Wen; Chunyuan Zhang (J. Supercomput., 2015)

Improve security and availability for cloud storage. - Shenling Liu; Chunyuan Zhang; Le Bo (CCIS, 2016)

Multikernel Recursive Least-Squares Temporal Difference Learning. - Chunyuan Zhang; Qingxin Zhu; Xinzheng Niu (ICIC (3), 2016)

Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2. - Johannes Langguth; Qiang Lan; Namit Gaur; Xing Cai; Mei Wen; Chunyuan Zhang (ICPADS, 2016)

Kernel Recursive Least-Squares Temporal Difference Algorithms with Sparsification and Regularization. - Chunyuan Zhang; Qingxin Zhu; Xinzheng Niu (Comput. Intell. Neurosci., 2016)

RVNet: A fast and high energy efficiency network packet processing system on RISC-V. - Yanpeng Wang; Mei Wen; Chunyuan Zhang; Jie Lin (ASAP, 2017)

Winograd Algorithm for 3D Convolution Neural Networks. - Zelong Wang; Qiang Lan; Hongjun He; Chunyuan Zhang (ICANN (2), 2017)

DCC: Distributed Cache Consistency. - Shenling Liu; Chunyuan Zhang; Yujiao Chen (ICPCSEE (2), 2017)

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. - Yuran Qiao; Junzhong Shen; Dafei Huang; Qianming Yang; Mei Wen; Chunyuan Zhang (NPC, 2017)

High Performance Implementation of 3D Convolutional Neural Networks on a GPU. - Qiang Lan; Zelong Wang; Mei Wen; Chunyuan Zhang; Yijie Wang (Comput. Intell. Neurosci., 2017)

FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. - Yuran Qiao; Junzhong Shen; Tao Xiao; Qianming Yang; Mei Wen; Chunyuan Zhang (Concurr. Comput. Pract. Exp., 2017)

Applying Detection Proposals to Visual Tracking for Scale and Aspect Ratio Adaptability. - Dafei Huang; Lei Luo 002; Zhaoyun Chen; Mei Wen; Chunyuan Zhang (Int. J. Comput. Vis., 2017)

Exploiting a depth context model in visual tracking with correlation filter. - Zhaoyun Chen; Lei Luo 002; Dafei Huang; Mei Wen; Chunyuan Zhang (Frontiers Inf. Technol. Electron. Eng., 2017)

A Highly Parallel and Scalable Motion Estimation Algorithm with GPU for HEVC. - Yun-gang Xue; Huayou Su; Ju Ren 002; Mei Wen; Chunyuan Zhang; Li-Quan Xiao (Sci. Program., 2017)

Parallel programming course development based on parallel computational thinking. - Juan Chen 001; Li Shen 007; Jianping Yin; Chunyuan Zhang (TURC, 2018)

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. - Junzhong Shen; You Huang; Zelong Wang; Yuran Qiao; Mei Wen; Chunyuan Zhang (FPGA, 2018)

High performance graph analytics with productivity on hybrid CPU-GPU platforms. - Haoduo Yang; Huayou Su; Qiang Lan; Mei Wen; Chunyuan Zhang (HP3C, 2018)

Multiple CNN-based Tasks Scheduling across Shared GPU Platform in Research and Development Scenarios. - Zhaoyun Chen; Lei Luo 002; Wei Quan 004; Yang Shi 008; Jie Yu 008; Mei Wen; Chunyuan Zhang (HPCC/SmartCity/DSS, 2018)

Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. - Junzhong Shen; Yuran Qiao; You Huang; Mei Wen; Chunyuan Zhang (ISCAS, 2018)

Design of Practical Experiences to Improve Student Understanding of Efficiency and Scalability Issues in High Performance Computing: (Abstract Only). - Juan Chen 001; Li Shen 007; Jianping Yin; Chunyuan Zhang (SIGCSE, 2018)

MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. - You Huang; Junzhong Shen; Yuran Qiao; Mei Wen; Chunyuan Zhang (IEICE Electron. Express, 2018)

HPGraph: High-Performance Graph Analytics with Productivity on the GPU. - Haoduo Yang; Huayou Su; Qiang Lan; Mei Wen; Chunyuan Zhang (Sci. Program., 2018)

Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. - Junzhong Shen; Deguang Wang; You Huang; Mei Wen; Chunyuan Zhang (DAC, 2019)

GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters. - Zhaoyun Chen; Lei Luo 002; Haoduo Yang; Jie Yu 008; Mei Wen; Chunyuan Zhang (DATE, 2019)

Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. - Junzhong Shen; Deguang Wang; You Huang; Mei Wen; Chunyuan Zhang (FPGA, 2019)

SWAP: a sliding window algorithm for in-network packet measurement. - Zijun Hang; Yang Shi 008; Mei Wen; Wei Quan 004; Chunyuan Zhang (HP3C, 2019)

SACC: Configuring Application-Level Cache Intelligently for In-Memory Database Based on Long Short-Term Memory. - Jiawei Fei; Yang Shi 008; Mei Wen; Chunyuan Zhang (HPCC/SmartCity/DSS, 2019)

TBSW: Time-Based Sliding Window Algorithm for Network Traffic Measurement. - Zijun Hang; Yang Shi 008; Mei Wen; Chunyuan Zhang (HPCC/SmartCity/DSS, 2019)

An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. - Deguang Wang; Junzhong Shen; Mei Wen; Chunyuan Zhang (ICPP, 2019)

Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. - Zhuang Cao; Huayou Su; Qianming Yang; Mei Wen; Chunyuan Zhang (INFOCOM Workshops, 2019)

Poster Abstract: Deep Learning Workloads Scheduling with Reinforcement Learning on GPU Clusters. - Zhaoyun Chen; Lei Luo 002; Wei Quan 004; Mei Wen; Chunyuan Zhang (INFOCOM Workshops, 2019)

Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. - Deguang Wang; Junzhong Shen; Mei Wen; Chunyuan Zhang (ISCAS, 2019)

KVSwitch: An In-network Load Balancer for Key-Value Stores. - Yang Shi 008; Jiawei Fei; Mei Wen; Chunyuan Zhang (ISCC, 2019)

Interleaved Sketch: Toward Consistent Network Telemetry for Commodity Programmable Switches. - Zijun Hang; Mei Wen; Yang Shi 008; Chunyuan Zhang (IEEE Access, 2019)

Application-Oriented Network Scheduling With Metaflow. - Yang Shi 008; Jiawei Fei; Mei Wen; Chunyuan Zhang (IEEE Access, 2019)

A Fast Approach for Generating Efficient Parsers on FPGAs. - Zhuang Cao; Huiguo Zhang; Junnan Li 002; Mei Wen; Chunyuan Zhang (Symmetry, 2019)

Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. - Minjin Tang; Mei Wen; Junzhong Shen; Xiaolei Zhao; Chunyuan Zhang (DAC, 2020)

Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. - Junzhong Shen; Mei Wen; Minjin Tang; Xiaolei Zhao; Chunyuan Zhang (FPGA, 2020)

Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. - Qixuan Cheng; Mei Wen; Junzhong Shen; Deguang Wang; Chunyuan Zhang (ICA3PP (1), 2020)

Optimized HybridSketch: More Efficient with Analysis and Algorithm. - Xiaolei Zhao; Mei Wen; Minjin Tang; Qun Huang 001; Chunyuan Zhang (ICA3PP (1), 2020)

HybridSketch: A Memory-centric Precise Approach for Flow Measurement. - Xiaolei Zhao; Mei Wen; Minjin Tang; Qun Huang 001; Chunyuan Zhang (ICC, 2020)

Towards High-Efficiency Data Centers via Job-Aware Network Scheduling. - Yang Shi 008; Mei Wen; Chunyuan Zhang (ICPP, 2020)

Efficient Mini-batch Training for Echo State Networks. - Chunyuan Zhang; Chao Liu; Jie Zhao (ICRAI, 2020)

Incremental Deployment of Programmable Switches for Sketch-based Network Measurement. - Yang Shi 008; Mei Wen; Chunyuan Zhang (ISCC, 2020)

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. - Zhuang Cao; Huayou Su; Qianming Yang; Junzhong Shen; Mei Wen; Chunyuan Zhang (IEEE Access, 2020)

Estimation of the parameters of a weighted nuclear norm model and its application in image denoising. - Hongyao Deng; Jinsong Tao; Xiuli Song; Chunyuan Zhang (Inf. Sci., 2020)

Efficient Parallel TLD on CPU-GPU Platform for Real-Time Tracking. - Zhaoyun Chen; Dafei Huang; Lei Luo 002; Mei Wen; Chunyuan Zhang (KSII Trans. Internet Inf. Syst., 2020)

Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. - Junzhong Shen; You Huang; Mei Wen; Chunyuan Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Deep Learning Research and Development Platform: Characterizing and Scheduling with QoS Guarantees on GPU Clusters. - Zhaoyun Chen; Wei Quan 004; Mei Wen; Jianbin Fang; Jie Yu 008; Chunyuan Zhang; Lei Luo 002 (IEEE Trans. Parallel Distributed Syst., 2020)

SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. - Jianchao Yang; Mei Wen; Minjin Tang; Junzhong Shen; Chunyuan Zhang (HPCC/DSS/SmartCity/DependSys, 2021)

Automatic mapping and code optimization for OpenCL kernels on FT-matrix architecture (WIP paper). - Xiaolei Zhao; Mei Wen; Zhaoyun Chen; Yang Shi 008; Chunyuan Zhang (LCTES, 2021)

Minibatch Recursive Least Squares Q-Learning. - Chunyuan Zhang; Qi Song; Zeng Meng (Comput. Intell. Neurosci., 2021)

Revisiting Recursive Least Squares for Training Deep Neural Networks. - Chunyuan Zhang; Qi Song; Hui Zhou; Yigui Ou; Hongyao Deng; Laurence Tianruo Yang (CoRR, 2021)

BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. - Jianchao Yang; Mei Wen; Junzhong Shen; Yasong Cao; Minjin Tang; Renyu Yang; Jiawei Fei; Chunyuan Zhang (ICCD, 2022)

Recursive Least Squares Policy Control with Echo State Network. - Chunyuan Zhang; Chao Liu; Qi Song; Jie Zhao (CoRR, 2022)

Recursive Least Squares for Training and Pruning Convolutional Neural Networks. - Tianzong Yu; Chunyuan Zhang; Yuan Wang; Meng Ma; Qi Song (CoRR, 2022)

Recursive Least Squares Advantage Actor-Critic Algorithms. - Yuan Wang; Chunyuan Zhang; Tianzong Yu; Meng Ma (CoRR, 2022)

Recursive least squares method for training and pruning convolutional neural networks. - Tianzong Yu; Chunyuan Zhang; Meng Ma; Yuan Wang (Appl. Intell., 2023)

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device. - Siqing Fu; Tiejun Li; Chunyuan Zhang; Hanqing Li; Sheng Ma; Jianmin Zhang; Ruiyi Zhang; Lizhou Wu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Cell DINO: End-to-End Cell Segmentation and Tracking with Transformer. - Wei Liao; Lei Luo; Changjian Wang; Chunyuan Zhang (BIBM, 2024)

AFMA-Track: Adaptive Fusion of Motion and Appearance for Robust Multi-object Tracking. - Wei Liao; Lei Luo; Chunyuan Zhang (ICPR (16), 2024)

Spin-NeuroMem: A Low-Power Neuromorphic Associative Memory Design Based on Spintronic Devices. - Siqing Fu; Tiejun Li; Chunyuan Zhang; Sheng Ma; Jianmin Zhang; Lizhou Wu (CoRR, 2024)

SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow. - Bo Wang 159; Sheng Ma; Shengbai Luo; Lizhou Wu; Jianmin Zhang; Chunyuan Zhang; Tiejun Li (ACM Trans. Design Autom. Electr. Syst., 2024)

NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices. - Siqing Fu; Lizhou Wu; Tiejun Li; Chunyuan Zhang; Sheng Ma; Jianmin Zhang; Yuhan Tang; Jixuan Tang (CoRR, 2025)