16-Mb synchronous DRAM with 125-Mbyte/s data rate. - Yunho Choi; Myungho Kim; Hyunsoon Jang; Taejin Kim; Seung-hoon Lee; Ho-cheol Lee; Churoo Park; Siyeol Lee; Cheol-soo Kim; Soo-In Cho; Ejaz Haq; J. Karp; et al. (IEEE J. Solid State Circuits, 1994)

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. - Churoo Park; Hoeju Chung; Yun-Sang Lee; Jaekwan Kim 003; JaeJun Lee; Moo Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; et al. (IEEE J. Solid State Circuits, 2006)

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (ESSCIRC, 2010)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs. - Jong-Pil Son; Jin Ho Kim; Woo Song Ahn; Seung Uk Han; Satoru Yamada; Byung-Sick Moon; Churoo Park; Hong-Sun Hwang; Seong-Jin Jang; Joo-Sun Choi; Young-Hyun Jun; Soo-Won Kim (IEICE Trans. Electron., 2011)