Time Redundant Fault-Location in Bit-Sliced ALU's. - Chwan-Chia Wu (IEEE Trans. Computers, 1987)

Fault modeling and reliability evaluations using artificial neural networks. - Chyun-Shin Cheng; Yen-Tseng Hsu; Chwan-Chia Wu (ICNN, 1995)

Performance evaluation for multiple DSSS systems with channel bands overlapped. - Ming-Heui Chen; Bih-Hwang Lee; Chwan-Chia Wu (PIMRC, 1996)

A synchronization model for multimedia presentation with critical overlap avoidance. - InHo Lin; Chwan-Chia Wu; Bih-Hwang Lee (MSE, 1998)