Compiler managed micro-cache bypassing for high performance EPIC processors. - Youfeng Wu; Ryan N. Rakvic; Li-Ling Chen; Chyi-Chang Miao; George Chrysos; Jesse Fang (MICRO, 2002)

On-Chip Interconnection Architecture of the Tile Processor. - David Wentzlaff; Patrick Griffin; Henry Hoffmann; Liewei Bao; Bruce Edwards; Carl Ramey; Matthew Mattina; Chyi-Chang Miao; John F. Brown III; Anant Agarwal (IEEE Micro, 2007)

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. - Shane Bell; Bruce Edwards; John Amann; Rich Conlin; Kevin Joyce; Vince Leung; John MacKay; Mike Reif; Liewei Bao; John F. Brown III; Matthew Mattina; Chyi-Chang Miao; et al. (ISSCC, 2008)

Application Suitability Assessment for Many-Core Targets. - Chris J. Newburn; Jim Sukha; Ilya Sharapov; Anthony D. Nguyen; Chyi-Chang Miao (ISC Workshops, 2016)