BIST controlled variable sense amp timing for 90nm embedded SRAM. - Ciaran J. Brennan; Steven Eustis; John Goss; A. Humphrey; Michael Ouellette; Jeremy Rowland; Michael Fragano (CICC, 2004)

Power network analysis for ESD robustness in a 90nm ASIC design system. - Ciaran J. Brennan; Joseph N. Kozhaya; Robert A. Proctor (CICC, 2004)

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. - Ciaran J. Brennan; Kiran V. Chatty; Jeff Sloan; Paul Dunn; Mujahid Muhammad; Robert Gauthier 002 (Microelectron. Reliab., 2007)

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs. - Ciaran J. Brennan; Shunhua Chang; Min Woo; Kiran V. Chatty; Robert Gauthier 002 (Microelectron. Reliab., 2007)