A high-speed, low latency RSA decryption silicon core. - Ciaran McIvor; Máire McLoone; John V. McCanny (ISCAS (4), 2003)

FPGA Montgomery Multiplier Architectures - A Comparison. - Ciaran McIvor; Máire McLoone; John V. McCanny (FCCM, 2004)

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. - Máire McLoone; Ciaran McIvor; John V. McCanny (FPT, 2004)

FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). - Ciaran McIvor; Máire McLoone; John V. McCanny (ISCAS (3), 2004)

High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. - Ciaran McIvor; Máire McLoone; John V. McCanny (FPT, 2005)

High-Speed Hardware Architectures of the Whirlpool Hash Function. - Máire McLoone; Ciaran McIvor; Aidan Savage (FPT, 2005)

Hardware Elliptic Curve Cryptographic Processor Over $ rm GF(p)$. - Ciaran McIvor; Máire McLoone; John V. McCanny (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function. - Máire McLoone; Ciaran McIvor (J. VLSI Signal Process., 2007)