A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. - Ciaran Toal; Sakir Sezer; Xing Yu (FCCM, 2003)

Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. - Brendan McAllister; Sakir Sezer; Ciaran Toal (FPL, 2003)

A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET. - Ciaran Toal; Sakir Sezer (IPDPS, 2003)

A 32-Bit SoPC Implementation of a P5. - Ciaran Toal; Sakir Sezer (ISCC, 2003)

Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling. - Sakir Sezer; Emi Garcia-Palacios; Ciaran Toal; Stephen Dawson (ICC, 2004)

Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access. - Emi Garcia-Palacios; Sakir Sezer; Ciaran Toal; Stephen Dawson (ICT, 2004)

The Implementation of Scalable ATM Frame Delineation Circuits. - Ciaran Toal; Sakir Sezer (ICT, 2004)

A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. - Sakir Sezer; Ciaran Toal; Emi Garcia; Victoria Stewart (IPDPS, 2004)

Exploration of GFP frame delineation architectures for network processing. - Ciaran Toal; Sakir Sezer (SoCC, 2004)

A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. - Ciaran Toal; Sakir Sezer (AICT/SAPIR/ELETE, 2005)

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch. - Stephen O'Kane; Sakir Sezer; Ciaran Toal (SoCC, 2005)

Investigation into programmability for layer 2 protocol frame delineation architectures. - Ciaran Toal; Sakir Sezer (IPDPS, 2006)

A VLSI GFP Frame Delineation Circuit. - Ciaran Toal; Sakir Sezer; Xin Yang 010 (ISVLSI, 2006)

Exploration of high performance frame processing architectures. - Ciaran Toal (2006)

FPGA-Based Lookup Circuit for Session-Based IP Packet Classification. - Motasem Abdelghani; Sakir Sezer; Emi Garcia; Jun Mu; Ciaran Toal (AHS, 2007)

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. - Ciaran Toal; Dwayne Burns; Kieran McLaughlin; Sakir Sezer; Stephen O'Kane (AHS, 2007)

An FPGA Based Memory Efficient Shared Buffer Implementation. - Dwayne Burns; Ciaran Toal; Kieran McLaughlin; Sakir Sezer; Mike Hutton; Kevin Cackovic (FPL, 2007)

Programmable CRC circuit architecture. - Ciaran Toal; Sakir Sezer; Xin Yang 010; Kieran McLaughlin; Dwayne Burns; Tiberiu Seceleanu (SoCC, 2007)

Design and Implementation of a Field Programmable CRC Circuit Architecture. - Ciaran Toal; Kieran McLaughlin; Sakir Sezer; Xin Yang 010 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Transmit and receive filter design for OFDM based WLAN systems. - Pei Xiao 001; Ciaran Toal; Dwayne Burns; Vincent F. Fusco; Colin Cowan (WCSP, 2010)

A 1Gbps FPGA-based wireless baseband MIMO transceiver. - Ciaran Toal; Sakir Sezer; Dwayne Burns; Pei Xiao 001; Vincent F. Fusco (SoCC, 2012)

Fully hardware based WFQ architecture for high-speed QoS packet scheduling. - Kieran McLaughlin; Dwayne Burns; Ciaran Toal; Colm McKillen; Sakir Sezer (Integr., 2012)