An adaptive PLL tuning system architecture combining high spectral purity and fast settling time. - Cicero S. Vaucher (IEEE J. Solid State Circuits, 2000)

A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. - Cicero S. Vaucher; Igor Ferencic; Matthias Locher; Sebastian Sedvallson; Urs Voegeli; Zhenhua Wang (IEEE J. Solid State Circuits, 2000)

Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters. - Johan van der Tang; Cicero S. Vaucher (ICECS, 2001)

A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-μm CMOS. - Domine M. W. Leenaerts; Cicero S. Vaucher; Henk Jan Bergveld; Michael Thompson; Kevin Moore (IEEE J. Solid State Circuits, 2003)

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS. - Remco C. H. van de Beek; Cicero S. Vaucher; Domine M. W. Leenaerts; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2004)

Phase noise in frequency divider circuits. - Melina Apostolidou; Peter G. M. Baltus; Cicero S. Vaucher (ISCAS, 2008)

Frequency Synthesizers. - Cicero S. Vaucher; Rick Booth (CICC, 2009)

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems. - Yikun Yu; Peter G. M. Baltus; Anton de Graauw; Edwin van der Heijden; Cicero S. Vaucher; Arthur H. M. van Roermund (IEEE J. Solid State Circuits, 2010)

A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications. - Juan F. Osorio; Cicero S. Vaucher; Bill Huff; Edwin van der Heijden; Anton de Graauw (ISSCC, 2011)

Smoothed Phase-Coded FMCW: Waveform Properties and Transceiver Architecture. - Utku Kumbul; Nikita Petrov; Cicero S. Vaucher; Alexander Yarovoy (IEEE Trans. Aerosp. Electron. Syst., 2023)

Automotive Radar Interference Mitigation using Phase-Coded FMCW Waveform. - Utku Kumbul; Nikita Petrov; Cicero S. Vaucher; Alexander Yarovoy (JC&S, 2024)