A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC. - Ckristian Duran; D. Luis Rueda; Giovanny Castillo; Anderson Agudelo; Camilo Rojas; Luis Chaparro; Harry Hurtado; Juan Romero; Wilmer Ramirez; Héctor Gómez; Javier Ardila; Luis E. Rueda G.; et al. (LASCAS, 2016)

Standard cell camouflage method to counter silicon reverse engineering. - Héctor Gómez; Ckristian Duran; Elkim Roa (ICCE, 2018)

A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller. - Hanssel Morales; Ckristian Duran; Elkim Roa (LASCAS, 2019)

Defeating Silicon Reverse Engineering Using a Layout-Level Standard Cell Camouflage. - Héctor Gómez; Ckristian Duran; Elkim Roa (IEEE Trans. Consumer Electron., 2019)

An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications. - Ckristian Duran; Megan Wachs; Luis E. Rueda G.; Albert Huntington; Javier Ardila; Jack Kang; Andres Amaya; Héctor Gómez; Juan Romero; Laude Fernandez; Felipe Flechas; Rolando Torres; et al. (CICC, 2020)

Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors. - Ckristian Duran; Hanssel Morales; Camilo Rojas; Annachiara Ruospo; Ernesto Sánchez 001; Elkim Roa (ISCAS, 2020)

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. - Trong-Thuc Hoang; Ckristian Duran; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISCAS, 2020)

Quick Boot of Trusted Execution Environment With Hardware Accelerators. - Trong-Thuc Hoang; Ckristian Duran; Duc-Thinh Nguyen-Hoang; Duc-Hung Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2020)

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). - Trong-Thuc Hoang; Ckristian Duran; Khai-Duy Nguyen; Tuan-Kiet Dang; Quynh Nguyen Quang Nhu; Phuc Hong Than; Xuan-Tu Tran; Duc-Hung Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEICE Electron. Express, 2020)

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (HCS, 2021)

AES Sbox Acceleration Schemes for Low-Cost SoCs. - Ckristian Duran; Héctor Gómez; Elkim Roa (ISCAS, 2021)

Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability. - Ckristian Duran; Elkim Roa (ISCAS, 2021)

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISOCC, 2021)

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Khai-Duy Nguyen; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (ISOCC, 2021)

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Trong-Thuc Hoang; Cong-Kha Pham (ISOCC, 2022)

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Trong-Thuc Hoang; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

A Unified NVRAM and TRNG in Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Cong-Kha Pham (IEEE Access, 2022)

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2022)

A Unified PUF and Crypto Core Exploiting the Metastability in Latches. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (Future Internet, 2022)

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration. - Ckristian Duran; Elkim Roa (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Ronaldo Serrano; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2023)

A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Khai-Duy Nguyen; Tetsuya Iizuka; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)

Hardware-Friendly Implementation of Physical Reservoir Computing with CMOS-based Time-domain Analog Spiking Neurons. - Nanako Kimura; Ckristian Duran; Zolboo Byambadorj; Ryosho Nakane; Tetsuya Iizuka (CoRR, 2024)

Fully-Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R-Based Layout Automation Framework. - Shuowei Li; Ckristian Duran; Ritaro Takenaka; Tetsuya Iizuka (IEEE Access, 2025)