Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. - Claire Fenouillet-Béranger; P. Perreau; S. Denorme; L. Tosti; François Andrieu; Olivier Weber; S. Barnola; C. Arvet; Y. Campidelli; Sébastien Haendler; R. Beneyton; C. Perrot; et al. (ESSCIRC, 2009)

Process dependence of BTI reliability in advanced HK MG stacks. - Xavier Garros; Mikaël Cassé; M. Rafik; Claire Fenouillet-Béranger; Gilles Reimbold; François Martin; Claudia Wiemer; F. Boulanger (Microelectron. Reliab., 2009)

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit. - Olivier Thomas; Jean-Philippe Noel; Claire Fenouillet-Béranger; Marie-Anne Jaud; J. Dura; P. Perreau; Frédéric Boeuf; François Andrieu; D. Delprat; F. Boedt; Konstantin Bourdelle; Bich-Yen Nguyen; et al. (ISCAS, 2010)

New parameter extraction method based on split C-V for FDSOI MOSFETs. - Imed Ben Akkez; Antoine Cros; Claire Fenouillet-Béranger; Frédéric Boeuf; Quentin Rafhay; Francis Balestra; Gérard Ghibaudo (ESSDERC, 2012)

Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET. - Carlos Navarro; Noel Rodriguez; Luca Donetti; Akiko Oliata; Francisco Gámiz; François Andrieu; Olivier Faynot; Claire Fenouillet-Béranger; Sorin Cristoloveanu (ESSDERC, 2012)

Novel back-biased UTBB lateral SCR for FDSOI ESD protections. - Yohann Solaro; Pascal Fonteneau; Charles-Alexandre Legrand; Claire Fenouillet-Béranger; Philippe Ferrari; Sorin Cristoloveanu (ESSDERC, 2013)

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. - Claire Fenouillet-Béranger; Bernard Previtali; Perrine Batude; Fabrice Nemouchi; Mikaël Cassé; Xavier Garros; Lucie Tosti; Nils Rambal; Dominique Lafond; Hugo Dansas; Luca Pasini; Laurent Brunet; et al. (ESSDERC, 2014)

Intermediate BEOL process influence on power and performance for 3DVLSI. - Hossam Sarhan; Sébastien Thuries; Olivier Billoint; Fabien Deprat; Alexandre Ayres De Sousa; Perrine Batude; Claire Fenouillet-Béranger; Fabien Clermidy (3DIC, 2015)

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. - Olivier Billoint; Hossam Sarhan; Iyad Rayane; Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Olivier Rozeau; Gerald Cibrario; Fabien Deprat; A. Fustier; Julien Michallet; Olivier Faynot; et al. (DATE, 2015)

Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization. - M. Azzaz; A. Benoist; Elisa Vianello; Daniele Garbin; Eric Jalaguier; Carlo Cagli; C. Charpin; Stefania Bernasconi; Simon Jeannot; T. Dewolf; G. Audoit; C. Guedj; et al. (ESSDERC, 2015)

From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges. - Olivier Billoint; Hossam Sarhan; Iyad Rayane; Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Olivier Rozeau; Gerald Cibrario; Fabien Deprat; Ogun Turkyilmaz; Sébastien Thuries; Fabien Clermidy (ISPD, 2015)

Towards high density 3D interconnections. - Séverine Cheramy; Amadine Jouve; Lucile Arnaud; Claire Fenouillet-Béranger; Perrine Batude; Maud Vinet (3DIC, 2016)

Impact of intermediate BEOL technology on standard cell performances of 3D VLSI. - Melanie Brocard; Guillaume Berhault; Sébastien Thuries; Fabien Clermidy; Perrine Batude; Claire Fenouillet-Béranger; Laurent Brunet; François Andrieu; Fabien Deprat; Joris Lacord; Olivier Rozeau; Gerald Cibrario; et al. (ESSDERC, 2016)

Opportunities brought by sequential 3D CoolCube™ integration. - Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Laurent Brunet; Vincent Mazzocchi; Cao-Minh Vincent Lu; Fabien Deprat; Jessy Micout; Bernard Previtali; Paul Besombes; Nils Rambal; François Andrieu; et al. (ESSDERC, 2016)

Recent advances in 3D VLSI integration. - Claire Fenouillet-Béranger; Perrine Batude; Laurent Brunet; Vincent Mazzocchi; Cao-Minh Vincent Lu; Fabien Deprat; Jessy Micout; M.-P. Samson; Bernard Previtali; Paul Besombes; Nils Rambal; François Andrieu; et al. (ICICDT, 2016)

Guidelines for intermediate back end of line (BEOL) for 3D sequential integration. - Claire Fenouillet-Béranger; S. Beaurepaire; Fabien Deprat; Alexandre Ayres De Sousa; Laurent Brunet; Perrine Batude; Olivier Rozeau; François Andrieu; Paul Besombes; M.-P. Samson; Bernard Previtali; F. Nemouchi; et al. (ESSDERC, 2017)

Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. - Jessy Micout; Quentin Rafhay; Xavier Garros; Mikaël Cassé; Jean Coignus; Luca Pasini; Cao-Minh Vincent Lu; Nils Rambal; Claire Fenouillet-Béranger; Laurent Brunet; G. Romano; R. Gassilloud; et al. (ESSDERC, 2017)

Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. - Melanie Brocard; Benoît Mathieu; Jean-Philippe Colonna; Cristiano Santos; Claire Fenouillet-Béranger; Cao-Minh Vincent Lu; Gerald Cibrario; Laurent Brunet; Perrine Batude; François Andrieu; Sébastien Thuries; Olivier Billoint (ISVLSI, 2017)

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. - François Andrieu; Perrine Batude; Laurent Brunet; Claire Fenouillet-Béranger; Didier Lattard; Sébastien Thuries; Olivier Billoint; Richard Fournel; Maud Vinet (ICICDT, 2018)

Role of synaptic variability in spike-based neuromorphic circuits with unsupervised learning. - Denys R. B. Ly; Alessandro Grossi; Thilo Werner; Thomas Dalgaty; Claire Fenouillet-Béranger; Elisa Vianello; Etienne Nowak (ISCAS, 2018)

Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. - Tadeu Mota Frutuoso; Jose Lugo-Alvarez; Xavier Garros; Laurent Brunet; Joris Lacord; Louis Gerrer; Mikaël Cassé; Edoardo Catapano; Claire Fenouillet-Béranger; François Andrieu; Fred Gaillard; Philippe Ferrari (IRPS, 2021)

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. - Tadeu Mota Frutuoso; Xavier Garros; Perrine Batude; Laurent Brunet; Joris Lacord; Benoit Sklénard; V. Lapras; Claire Fenouillet-Béranger; M. Ribotta; A. Magalhaes-Lucas; J. Kanyandekwe; R. Kies; et al. (VLSI Technology and Circuits, 2022)

Radar-Based Human Activity Acquisition, Classification and Recognition Towards Elderly Fall Prediction. - Claire Fenouillet-Béranger; Alexandre Bordat; Mohamed Amine Khelif; Petr Dobiás; Ngoc-Son Vu; Julien Le Kernec; David Guyard; Olivier Romain (DSD, 2023)

First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. - J. Luge-Alvarez; J. B. David; Alexandre Siligaris; Vincent Puyal; G. Moritz; Tadeu Mota Frutuoso; V. Lapras; Claire Fenouillet-Béranger; Laurent Brunet; P. Vincent; Didier Lattard; Xavier Garros; et al. (VLSI Technology and Circuits, 2024)

Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. - Claire Fenouillet-Béranger; Laurent Fesquet; Rihab Chouk; Gabriel Pares; Baudoin Martineau; Marie Claire Cyrille; Thierry Poiroux; Olivier Billoint; Dominique Noguet (DDECS, 2025)

Fast CV MSM Technique for Comprehensive Analysis of Bulk Trapping in Low-K Carbon-Doped Dielectrics. - Tadeu Mota Frutuoso; William Vandendaele; A. Bond; F. Bringuier; V. Lapras; Marie Claire Cyrille; Claire Fenouillet-Béranger; B. Duriez; Xavier Garros (IRPS, 2025)