An 8-bit multitask micropower RISC core. - Jean-Félix Perotto; C. Lamothe; Claude Arm; Christian Piguet; Evert Dijkstra; Stefan Fink; Eduardo Sanchez; J.-P. Wattenhofer; M. Cecchini (IEEE J. Solid State Circuits, 1994)

Low-Power Embedded Microprocessor Design. - Christian Piguet; Thierry Schneider; Jean-Marc Masgonty; Claude Arm; Serge Durand; M. Stegers (EUROMICRO, 1996)

Low-power design of 8-b embedded CoolRisc microcontroller cores. - Christian Piguet; Jean-Marc Masgonty; Claude Arm; Serge Durand; Thierry Schneider; Flavio Rampogna; Ciro Scarnera; Christian Iseli; Jean-Paul Bardyn; R. Pache; Evert Dijkstra (IEEE J. Solid State Circuits, 1997)

Double-Latch Clocking Scheme for Low-Power I.P. Cores. - Claude Arm; Jean-Marc Masgonty; Christian Piguet (PATMOS, 2000)

Low-power low-voltage library cells and memories. - Christian Piguet; Jean-Marc Masgonty; Stefan Cserveny; Claude Arm; Pierre-David Pfister (ICECS, 2001)

The ultra low-power wiseNET system. - Amre El-Hoiydi; Claude Arm; Ricardo Caseiro; Stefan Cserveny; Jean-Dominique Decotignie; Christian C. Enz; Frédéric Giroud; Steve Gyger; E. Leroux; Thierry Melly; Vincent Peiris; Franz-Xaver Pengg; et al. (DATE, 2006)

Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core. - Claude Arm; Steve Gyger; Jean-Marc Masgonty; Marc Morgan; Jean-Luc Nagel; Christian Piguet; Flavio Rampogna; Patrick Volet (ESSCIRC, 2008)

An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications. - Pierre-François Rüedi; Pascal Heim; Steve Gyger; François Kaess; Claude Arm; Ricardo Caseiro; Jean-Luc Nagel; Silvio Todeschini (ISSCC, 2009)

Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core. - Claude Arm; Steve Gyger; Jean-Marc Masgonty; Marc-Nicolas Morgan; Jean-Luc Nagel; Christian Piguet; Flavio Rampogna; Patrick Volet (IEEE J. Solid State Circuits, 2009)

A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks. - Erwan Le Roux; Nicola Scolari; Budhaditya Banerjee; Claude Arm; Patrick Volet; Daniel Sigg; Pascal Heim; Jean-Félix Perotto; François Kaess; Nicolas Raemy; Alexandre Vouilloz; David Ruffieux; et al. (ISSCC, 2010)

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. - Marc Pons 001; Thanh-Chau Le; Claude Arm; Daniel Séverac; Jean-Luc Nagel; Marc-Nicolas Morgan; Stéphane Emery (ESSCIRC, 2016)

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. - Jian Deng; Jean-Luc Nagel; Loïc Zahnd; Marc Pons 001; David Ruffieux; Claude Arm; Pascal Persechini; Stéphane Emery (ISLPED, 2019)